Blog Review: Oct. 5


Mentor's Michael White explores why established nodes are experiencing such an unexpectedly long lifespan and how that is driving new challenges for designers. Cadence's Ann Keffer checks out the history of Ethernet and how it won the battle to become the dominant network protocol. Is your IoT device fueling a botnet? Vulnerable firmware on internet connected devices was behind one of the... » read more

Blog Review: Aug. 5


Fresh from the July 2015 Type-C InterOp Event, where USB engineers wheel a prototype on a cart from hotel room to hotel room, testing interoperability, Synopsys' Morten Christiansen says Type-C has arrived. Mentor's Colin Walls discusses the reasons to tackle embedded software development with a bottom-up approach. In their latest video, Cadence's Kishore Kasamsetty discusses why choose L... » read more

Blog Review: May 20


FinFETs change the equation for power optimization, says Mentor's Vincent Lebars – and while companies are attacking some power gains, there is much more to be had doing datapath optimization within the place and route flow. Cadence's Richard Goering talks with Oz Levia about the future direction of formal and its integration into other product lines now that the merger between Cadence and... » read more

Blog Review: May 6


How do you choose between bulk planar transistors, FinFETs, and FD-SOI? Cadence's Richard Goering got some answers during a session at the Electronic Design Process Symposium. Check out the Q&A in the second part, too. Synopsys' Michael Posner tackles a question about the differences between a prototyping bridge and hybrid prototypes and the limitations each has to solve various kinds of... » read more

Blog Review: Nov. 12


ARM's Eoin McCann provides a primer to software-defined networking, which uses a higher level of abstraction to create a centralized controller. This is a new twist on networking—with a bit of deja vu thrown in. Mentor's Matthew Ballance points to a perfect storm for verification—shrinking features, more layers and more embedded processors. He has some tips for how to deal with all of t... » read more

The Week In Review: Design


Tools Synopsys uncorked the next version of its verification tool, which includes static and formal verification, new debug capabilities, and low-power and X-propagation simulation. The company says the new tool offers up to 5X performance improvement. Cadence rolled out a new version of its verification solution for designs using ARM’s interconnect IP, speeding up verification and analys... » read more

The Week In Review: System-Level Design


Cadence bought TranSwitch’s high-speed interface IP assets. TranSwitch, which made chips for communications equipment, filed for bankruptcy in November. (The company’s Web site is no longer active.) Cadence also won a deal with Microsoft, which will use Tensilica processors in the new Xbox One audio subsystem. And Cadence rolled out HiFi Audio Tunneling for Android, which takes advantage of... » read more

President Obama Visits Applied Materials


By John Kania [caption id="attachment_8398" align="alignnone" width="518" caption="Applied Materials CEO Mike Splinter with President Barack Obama as they tour the Austin manufacturing clean room and hear from Applied employee Nilam D. Bhakta-Sahib about the complex chip making process. "][/caption] President Obama rode Air Force One into Austin, Texas, to shine a spotlight on the import... » read more