tag: Wide I/O

Memory Gets Smarter
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Look inside any complex SoC these days and the wiring congestion around memory is almost astounding. While the number of features on a chip is increasing, they are all built around the same memory modules. Logic needs memory, and in a densely packed semiconductor, the wires that connect the myriad logic blocks are literally all over the memory. This is made worse by the fact ... » read more

Multicore: Is More Better?
By Frank Ferro - 30 May, 2013 - Comments: 0

By Frank Ferro Two cores are better than one, right? It reminds me of those AT&T commercials where they ask the kids, “Who thinks two is better than one?” And of course the kids all yell, two! In another version of the commercial they ask; “What’s better, doing two things at once or just one?” And again they all yell, two! Well, this is a good summary or of last week’s Multicor... » read more

Experts At The Table: Latency
By Ed Sperling - 01 Feb, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance engineering sat down to discuss latency with Chris Rowen, CTO at Tensilica; Andrew Caples, senior product manager for Nucleus in Mentor Graphics’ Embedded Software Division; Drew Wingard, CTO at Sonics; Larry Hudepohl, vice president of hardware engineering at MIPS; and Barry Pangrle, senior power methodology engineer at Nvidia. What follows are exce... » read more

Keeping Pace With Moore’s Law
By Ann Mutschler - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As the number of transistors doubles with each move to a smaller manufacturing process technology, there are questions as to whether the current cadre of place and route tools will be able to keep in lock step. Have no fear, assured Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “For the increase in densities that we get with... » read more

Welcome To The ‘Probably Good Die’ Era
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus In today’s systems, consumers want more performance and bandwidth with a longer battery life. Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the pa... » read more

Straight Talk On 3D TSVs
By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss 3D device challenges and applications with John Lau, a fellow at the Industrial Technology Research Institute (ITRI), a research organization in Taiwan. SMD: What is ITRI doing in 3D TSVs? Lau: At ITRI we have developed the world’s first Applied Materials’ 300mm (3D TSV) integration line. The line was comple... » read more

Mobile Memory Madness
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus The insatiable thirst for more bandwidth in smartphones, tablets and other devices has prompted an industry standards body to revamp its mobile memory interface roadmap. As part of the changes, the Joint Electron Devices Engineering Council (JEDEC) has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architectur... » read more

Where Does It Hurt?
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The IC design industry is feeling a new kind of pain—this one driven by uncertainty over architectural shifts, new ecosystem interactions and new ways to account for costs. As mainstream ICs move from 50/45/40nm to around 32/28/22nm, there are only two choices for design teams—continue shrinking features or stack dies. In many cases, the ultimate solution may be a combina... » read more

Experts At The Table: Stacked Die Reality Check
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of market... » read more

Experts At The Table: Mobile Design Challenges
By Ed Sperling - 21 Oct, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation. ... » read more

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