Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Formal Analysis Of X Propagation


Verifying the absence of undefined signal values in a design is in general a hard problem. Formal 4-state logic analysis offers a powerful solution. This white paper discusses X-related verification issues, and how advanced 4-state formal analysis solves them. This white paper covers the 360 DV-Verify product. To read more, click here. » read more

The New Face Of Formal


Semiconductor Engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager of R&D in the verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphic... » read more

Delicate Balance


By Joe Hupcey III It’s not surprising that power optimization is a critical part of today’s complex designs. Unbeknownst to most consumers is an underlying methodology that every design engineer must follow to make sure a consumer device meets the power requirements of the consumer—even if the consumer doesn’t realize they’re demanding it. The situation in industrial products, suc... » read more