Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

The Week In Review: Design/IoT


M&A Tessera boosted its 2.5D and 3D-IC capabilities with the acquisition of Ziptronix. The $39 million cash purchase adds a low-temperature wafer bonding technology platform, which has been licensed to Sony for volume production of CMOS image sensors. Numbers Semico Research forecasts that the SoC market will approach $200 billion by 2019. According to its analysis, average die are... » read more

Options And Hurdles Come Into Focus For 3D Stacking


By Mark LaPedus The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market. There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs. The enormous risk to bring ... » read more