Now that EUV has hit another hiccup, it’s time to start polishing your multi patterning skills.
Mentor Graphics’ David Abercrombie shows how multi patterning is supposed to be done, and what sorts of problems can crop up along the way. Now that EUV has hit another hiccup, the semiconductor industry has little choice.
Negative bias temperature instability could force chipmakers to change course on materials.
Autonomous racing; Earth Day engineering; cybersecurity and the military; FPGA verification effectiveness; PCB design, the quiz show; all about Pulse Code Modulation; ARM’s early years; solid state microwaves.
Experts at the table, part 2: FinFETs on FD-SOI, comparisons with stacked die and system-in-package, and what it takes to do a design on FD-SOI versus a finFET at 14/16nm.
Foundries split over 1D and 2D layout schemes, creating tough choices for chipmakers involving performance, area and other options.
Experts at the table, part 3: Cost and performance differences between FD-SOI, finFETs and 28nm LP processes; predictions about FD-SOI’s longevity; what’s after 28nm.
Fab equipment startup targets modular 2D multi-column array.
Longer manufacturing time plus constrained capacity means designs now have to be finished earlier than ever before—sometimes months earlier.
Problems and an early look at best practices that will be required for dealing with the next level of complexity.
IBM job cuts; Applied-TEL update; Lam’s results and outlook; CapEx race.
It costs nearly three times more to design a finFET-based chip than a 28nm planar chip, and it takes more than twice as long to get working silicon.
Move adds custom analog and mixed signal capability for Mentor, positions company for IoT.
Intel to delay 10nm?; who won Apple’s foundry biz?; Moore’s Law celebration; material world.