The First Fully Configurable Cache-Coherent Interconnect Solution For SoCs

How to manage shared resources to ensure coherency.

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The last few decades have seen a massive growth in the number of CPU cores, computing clusters and other IP blocks in a SoC. This massive growth along with the need for complex chip integration has driven the need for sophisticated interconnects. SoC architects have employed a variety of methods from buses to crossbars to handcrafted NoCs with Lego-like blocks with varying degrees of success. The increase in the number of agents accessing a critical resource like memory has also meant the shared data needs to be managed to ensure cache coherency.

This white paper introduces a new solution that uses a number of proven algorithms to optimize interconnects, providing a scalable, high performance, correct-by-construction Network-on-Chip (NoC) solution. To read more, click here.