The Future of Package Design Verification: Assembly Design Kits

How to create a 2.5D and 3D-IC package with lower risk of failure.

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Chip design companies and package assembly houses have no unified signoff verification process to ensure that an IC package meets manufacturability and performance requirements. Packages need a process that confirms the disparate products they contain can be manufactured within a single package. Mentor Graphics collaborated with Qualcomm and STATS ChipPAC to develop a prototype assembly design kit (ADK) for 2.5/3D IC packages. While creating an ADK is a non-trivial effort, and requires cooperation and collaboration between design houses, assembly houses, and EDA vendors, using an ADK can reduce risk of package failure, while also reducing turnaround time for both the component providers and assembly houses.

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