The Week In Review: Design

ARM and Synopsys acquire; heterogeneous cache coherent interconnects; Aldec reaches out; big data for EDA; place-and-route update; ARM & 10nm finFET; Mentor & Synopsys financials.



ARM acquired embedded computer vision and imaging technology company Apical Ltd. for $350 million in cash. According to ARM, the company’s technology has been utilized in more than 1.5 billion smartphones and in about 300 million other consumer and industrial devices.

Synopsys acquired Simpleware, a provider of software products for converting 3D scan data into high-quality computer models used for engineering design and simulation. Terms of the deal were not disclosed.


Arteris unveiled an architecture that allows designers to configure a distributed heterogeneous cache coherent interconnect with multiple fully-coherent agent ports in a protocol-agnostic manner. Included features allow selection of the number of coherent agents and memory interface ports, numbers and sizes of configurable snoop filters, and number and sizes of proxy caches and “victim” last-level caches.

Aldec expanded its reach with an announcement that its FPGA verification tools, from design and test planning through simulation, emulation, and prototyping, are now available for ASIC designs.

Ansys launched a new product based on big data techniques to handle the vast amounts of data created by engineering simulation. According to the company, the SeaHawk tool provides significant improvements in simulation coverage, turnaround times, and analysis flexibility, with early users seeing an average of 5% reduction in die size.

Synopsys updated its IC Compiler II place-and-route tool with QoR-focused enhancements including congestion-driven restructuring, power-aware concurrent-clock-and-data optimizations, advanced full-flow power optimization and improvements in route-guided design closure. The tool was adopted by HiSilicon, Movidius, and Toshiba.

Ansys also released a new version of its free engineering simulation suite for students, as well as adding a new easy-to-use multiphysics engineering simulation environment to the package.


ARM announced the first multicore, 64-bit ARM v8-A processor test chip based on TSMC’s 10FinFET process technology. Tape out of the test chip completed in Q4 2015. According to ARM, simulation benchmarks show power and efficiency gains relative to TSMC’s 16FinFET+ process.

Deals & Certifications

Fog removal software from Uurmi Systems, targeted at automotive and camera markets, is now available on Cadence’s Tensilica Vision DSP. The software removes fog present in the photo and applies correction to improve the image using a spatial diffusion filtering-based approach.

Imagination is working with the Debian Project to accelerate development of the open source Debian operating system for the 64-bit MIPS architecture. Imagination is donating several high-performance SDNA-7130 appliances to the Debian Project for port development and maintenance.

Synopsys’ Custom Compiler tool has been enabled by Samsung for 14nm LPP and LPC FinFET production.


Synopsys reported second quarter financial results for 2016 with revenue of $605 million, up 8.6% from the second quarter last year. On a GAAP basis, net income per share stood at $0.45, up 28.6% from Q2 2015. Non-GAAP EPS was $0.81, up 19.1%.

Mentor Graphics reported first quarter 2017 financial results with revenue of $228 million, down 16.4% from the same quarter last year. On a GAAP basis, there was a net loss per share of $0.12, down from a loss of $0.08 the year before. On a non-GAAP basis, earnings per share were $0.02, down 92.9% from Q1 2016’s $0.28.