Three new processors; high-level synthesis; secure cores; cycle accurate models; deals.
Mentor Graphics uncorked the latest version of its Catapult high-level synthesis platform, adding a formal-based C Property Checker tool to automatically identify and formally prove hard-to-find issues like uninitialized memory, divide by 0, and array bounds errors in the users’ HLS C++/SystemC model.
ARM unveiled the Cortex-A73 and Mali-G71 processors. According to ARM, the graphics processor, based on the new Bifrost architecture, provides a 50% increase in graphics performance, a 20% increase in power-efficiency and 40% more performance per mm2. The Cortex-A73, optimized for 10nm FinFET process technology, provides 30% uplift in sustained performance and power efficiency over the Cortex-A72. The core has been licensed by HiSilicon, Marvell, and Mediatek, among others. Cadence made available rapid adoption kits for the two processors, which can utilize Artisan physical IP and ARM POP IP, as well as working with ARM to develop a 10nm methodology. Synopsys also delivered a reference implementation for Cortex-A73 with Artisan standard cells, memories and ARM POP IP as well as announcing successful early adopter tape-outs for both processors.
Synopsys revealed its newest generation of processor cores optimized for embedded vision applications requiring high definition resolutions, with up to 100X higher performance on common vision processing tasks than the previous generation. The fully programmable and configurable embedded vision processors integrate one, two or four vision CPU cores and a programmable convolution neural network engine which operates in parallel with the vision CPUs.
Andes Technology will incorporate Intrinsic-ID’s Physical Unclonable Functions (PUF) for its secure CPU/MCU cores. Based on the properties of SRAM memory, Intrinsic-ID’s PUF technology uses random patterns to differentiate chips from each other and enable the extraction of unique identifiers and cryptographic keys.
ARM expanded the availability of its cycle-accurate model portfolio to integrate with SystemC environments including offerings from Cadence and Synopsys. All future Cycle Models will be released with SystemC support.
Dream Chip Technologies licensed Arteris’ FlexNoC interconnect IP, along with additional data protection features required to obtain higher ISO 26262 certification, for use in the European Commission / ENIAC THINGS2DO automotive ADAS reference development platform project.
Cadence’s Analog Mixed-Signal model-based methodology was adopted by Hitachi for one of its largest mixed-signal design projects, which said reduced full-chip simulation time to 30 minutes.
Mentor won a deal with Samsung Foundry, which will use production Calibre and Tessent platforms in its Closed-Loop DFM solution to identify IC design patterns that are most likely to impact manufacturing yield.
NetSpeed selected Magillem’s IEEE1685 test suite to certify that the IP-XACT files generated by its network-on-chip platform are compliant with the industry standard.
Avnet ASIC Israel, a provider of SoC design, layout and manufacturing services, standardized on Synopsys’ Design Compiler Graphical RTL synthesis solution, citing a savings of two to three weeks in the overall RTL-to-GDSII schedule.
STMicroelectronics deployed Cadence’s Virtuoso platform for its SmartPower technologies, citing improved custom routing quality and performance and significantly reduced block-planning and pin-optimization time using special pin groups and guide constraints.