Mentor unites Questa and Veloce for productivity gain; ARM compiler improves code quality, performance and power efficiency on ARM processors; Global Unichip licenses Arteris FlexNoC; LEONI expands use of Mentor Graphics wire harness software; Rambus division Cryptography Research inks license agreement with Fairchild.
Mentor Graphics announced its Enterprise Verification Platform (EVP) that pulls together the company’s Questa verification technologies with Veloce OS3 global emulation resourcing technology, and the Visualizer debug technology into what it says is a globally accessible, high-performance datacenter resource. The system is aimed at global resource management and supports project teams around the world, for maximizing both user productivity and total verification return on investment. The company claims it delivers performance and productivity improvements from 400X to 10,000X and eliminates the barriers to hardware acceleration by combining the functionality and observability of simulation-based verification with the speed of emulation.
To improve code quality, performance and power efficiency of software on its processors, ARM reported that version 6 of the ARM Compiler — the reference code generation toolchain for the ARM architecture — is now available; it adopts the Clang and LLVM open source compiler framework, channeling contributions from the whole ARM Partnership.
Network-on-chip interconnect supplier Arteris said that Global Unichip has licensed its FlexNoC fabric IP for use in its 16nm SoC IP verification platform. Ching-Che Liang, senior VP of R&D at Global Unichip said the evaluation of Arteris FlexNoC was extremely quick, and received very positive results in routing and timing closure and that using FlexNoC creates unique time and cost advantages for it and its customers.
LEONI said it is expanding its use of Mentor Graphics’ Capital software throughout the world, driven in part by increasing adoption of the modular approach to wire harness configuration management, also known as customer-specific or zero give-away harnessing.
Cryptography Research, a division of Rambus announced that it has signed a patent license agreement with Fairchild Semiconductor. This allows for the use of Cryptography Research’s patented inventions in Fairchild’s ICs in order to make Fairchild’s tamper-resistant ICs more securely protected against differential power analysis and related attacks. The license also covers software developed by Fairchild’s customers when utilized on Fairchild’s licensed integrated circuits.