The Week In Review: Design

Planar HBM2 PHY; eFPGA on TSMC 16nm; ultrasound touch sensing.

popularity

IP

eSilicon launched 14nm FinFET and 28nm planar HBM Gen2 Hardened PHY. It supports up to 256Gbytes/sec bandwidth with 8x128b channels at 2Gbps per I/O, and the integrated I/O supports up to 2Gbps DDR operation across a 4mm interposer channel. The PHY was developed on Samsung 14LPP and TSMC 28HPC technologies.

Flex Logix designed a high-performance embedded FPGA IP core for TSMC 16FF+ and 16FFC, with performance for wide, single-stage logic around ~1GHz at worst case PVT conditions. The IP targets networking, base station and data center chips and can be arrayed to build control logic blocks from ~100 LUTs to ~3000 LUTs. It is expected to be validated in early 2017.

Deals

Sentons licensed Cadence’s ConnX BB32EP DSP for a new ultrasound-based sensing technology to replace capacitive touch in mobile devices. Sentons says the technology allows for touch sensing on metal and curved surfaces, as well as force and pressure sensing without surface deformation.

Miscellaneous

Imagination’s Ensigma Explorer wireless communications IP achieved Wi-Fi CERTIFIED status. Certification was achieved via a reference design using the CxT200 chip.

NXP will add five additional years to the longevity program for six S08 8-bit microcontrollers: S08QG, S08QD, S08SF, S08SH, S08AC, and S08FL.

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