The Week In Review: Design/IoT

IEEE’s roadmap; AMS standard; upgrades from Cadence; PCB platform; Energy Processing Unit; Hybrid Memory Cube VIP; Ansys’ Q1 financials.

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Standards

The IEEE launched the International Roadmap for Devices and Systems (IRDS), effectively setting the industry agenda for future silicon benchmarking and adding metrics that are relevant to specific markets rather than creating the fastest general-purpose processing elements at the smallest process node. For more on the IRDS, check out Ed Sperling’s analysis.

Accellera’s SystemC AMS standard has been released by the IEEE-SA as IEEE 1666.1-2016. It is available for download at no charge under the Accellera-sponsored IEEE Get Program. The standard focuses on design and modeling of analog/mixed-signal applications at higher levels of design abstraction. Extensions define a uniform and standardized modeling approach that can be used in combination with digitally-oriented SystemC-based design methods.

Tools

Cadence announced a number of product updates at CDNLive EMEA: Its OrCAD portfolio added technology for integrated rigid-flex planning, design and real-time visualization, as well as built-in translators that enable direct design imports from select EDA vendors, while Allegro added comprehensive in-design inter-layer checking technology and a new dynamic concurrent team design capability. The company also released its highest-performing vision/imaging processor, which includes new instructions, increased math throughput and other enhancements increase performance by up to 4X compared to the previous DSP.

Mentor Graphics uncorked a comprehensive product-creation platform based on PADS PCB software, integrating tools for power integrity analysis as well as thermal simulation and electronic cooling.

IP

Sonics unveiled an Energy Processing Unit (EPU) based on the company’s ICE-Grain Power Architecture, designed to optimize the idle moments of SoC components. The EPU incorporates intelligent event and switching controllers and an automated SoC power design methodology integrated with standard EDA functional and physical tool flows.

Synopsys debuted verification IP for Micron’s Hybrid Memory Cube (HMC) architecture. The VIP is integrated with Synopsys’ memory-aware graphical debug solution.

Deals

NetSpeed Systems opened operations in Taiwan where Maojet Technology will be the authorized distributor for its on-chip network IP. Dedicated support will be provided through NetSpeed personnel in Taipei.

Fabless ASIC/SoC and IP provider Faraday Technology Corporation used Cadence’s OrbitIO interconnect designer and SiP Layout, which it said reduced packaging design time by 60% over their previous methodology.

Interoperable Process Design Kits are now available for Dongbu HiTek foundry customers using Synopsys’ Custom Compiler. The iPDKs initially support Dongbu HiTek’s mixed-signal process nodes at 0.11-micron as well as BCDMOS technology at 0.18-micron node operating at 1.8V/5V and up to 30V with LDMOS.

General Electric expanded its licensing deal with Ansys to accommodate GE’s November 2015 acquisition of Alstom’s Power and Grid businesses, and from product development into operations.

Numbers

Ansys released first quarter financial results, with revenues of $225.9 million, up 4% from Q1 last year. On a GAAP basis, earnings per share stood at $0.63 (up 3% from Q1 2015) and non-GAAP EPS of $0.77 (no change). Recurring revenue, comprised of lease license and maintenance revenue, totaled 78% of revenue for the first quarter.

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