Cadence adds electrically aware layout; Mentor wins deal with Realtek; Synopsys wins deal with Fujitsu.
By Ed Sperling
Cadence rolled a new version of its layout suite of tools for electrically aware designs, allowing design teams to check on electrical issues while the layout is being done. The company says this can reduce circuit design time by up to 30%, in addition to optimizing for performance and area. Cadence also announced a deal with Global Unichip, which successfully taped out a 20nm test chip using Cadence’s DFM tools. Cadence has been working closely with TSMC, which in turn has a big stake in Global Unichip, a design services provider. In addition, TSMC will deliver SKILL-based process design kits to support Cadence’s custom and analog design tools.
Mentor Graphics won a deal with Taiwan’s Realtek Semiconductor, which is using Mentor’s electrical circuit checks signoff tool to protect against electrostatic discharge. Realtek makes a wide variety of chips for communications, peripherals and multimedia applications.
Synopsys won a deal with Fujitsu Laboratories, which is using Synopsys’ processor design tool for a 3G/LTE multi-mode modem. The modem consumes 20% less power than commercially available DSP IP, according to the companies.
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