The Week In Review: Manufacturing

22nm bulk vs. FD-SOI; ECD for packaging; Coventor joins photonics group.

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Chipmakers
At this week’s TSMC Technology Symposium in San Jose, Calif., TSMC rolled out a dizzying array of new processes and technologies. Perhaps the most surprising announcement was a 22nm bulk CMOS process, which is geared for ultra low-power planar chips. The technology will compete against a 22nm FD-SOI technology from GlobalFoundries. Stay tuned. The battle has just begun.

As expected, TSMC rolled out a new derivative of its 16nm finFET process, a 12nm finFET process. At the high-end, TSMC will shortly ramp its 10nm finFET process. Separately, the company is readying its 7nm finFET process, with initial tape outs slated for May. Then, as expected, TSMC is working on a second iteration of 7nm using extreme ultraviolet (EUV) lithography.

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Samsung said that its 10nm finFET production ramp is on track with “steady high yield” to meet customer needs on schedule. Samsung has shipped more than 70,000 silicon wafers of its first-generation 10nm LPE (Low Power Early) to date. The company began shipping 10LPE last October.

Synopsys and United Microelectronics Corp. (UMC) are working together to enable Synopsys Custom Compiler and Laker custom design tools to be used with UMC’s 14nm finFET process. This enables new and validated PDKs for UMC’s 14nm process.

T.J. Rodgers, founder and former CEO and president of Cypress Semiconductor, has released a detailed presentation for Cypress stockholders, highlighting what he believes are the company’s conflict of interest and governance problems.

Manufacturing
Applied Materials has been recognized as a 2017 World’s Most Ethical Company by the Ethisphere Institute, a global leader in defining and advancing the standards of ethical business practices. In addition, Applied Materials has rolled out Nokota, a new system that handles electrochemical deposition for wafer-level packaging. These range from flip-chip and wafer-level chip-scale packages to 2D and 3D fan-out, 2.5D interposer designs, and through-silicon vias (TSVs).

The American Institute for Manufacturing Integrated Photonics (AIM Photonics), a public-private partnership advancing the nation’s photonics manufacturing capabilities, has announced that Coventor is the latest member of the group. Coventor will provide access to its 3D modeling technology to improve the performance and manufacturability of complex, integrated photonic designs.

Cadence Design Systems, Coventor, X-FAB and Reutlingen University – joint sponsors of a worldwide MEMS design contest – has announced the commencement of the design phase of the contest.

STATS ChipPAC has shipped 1.5 billion fan-out wafer level packages, also known in the industry as embedded Wafer level Ball Grid Array (eWLB). In high volume production for over seven years, STATS ChipPAC has led the industry in fan-out technology.

Market research
North America-based manufacturers of semiconductor equipment posted $1.97 billion in billings worldwide in February of 2017, according to SEMI. The billings figure is 6.1% higher than the final January 2017 level of $1.86 billion, and is 63.8% higher than the February 2016 billings level of $1.20 billion.

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The Week In Review: Manufacturing
No Semicon Russia; Intel supplier awards; fingerprint sensors; self-driving cars.