Three Power-Saving Techniques Using PCI Express IP

Strategies for fast resume times while working with power-efficient SoCs.

popularity

The increasing data traffic between devices in a computing application environment is causing a large power footprint, and for that reason designers are looking for ways to lower the power consumption of their SoCs during sparse or idle times. The smaller, battery-powered devices are often idle and in deep sleep modes, but these deep power saving modes come at the cost of slow resume times to switch back to normal operating mode. This paper uses PCI Express IP as an example to describe three power saving techniques and how designers are using the protocol’s and design tools’ power management features to deliver power-efficient SoCs for devices requiring fast resume times.

Outline

  • Clock Gating Techniques — Synthesis Tools
  • Clock Gating Techniques — PCI Express IP
  • Clock Gating and Power Gating Techniques — PCI Express Protocol