Orders of magnitude faster verification performance using the Cadence Incisive 13.2 Platform.
It’s a persistent theme: engineers are expected to do more with the same or fewer resources. Meantime, designs continue to grow larger and more complex. Studies have shown that verification continues to consume up to 70% of the IC development cost in each advanced node. Cadence’s R&D teams designed the latest version of the Incisive® functional verification platform with these pressures in mind.
The Incisive 13.2 platform sets a new standard for overall verification system-on-chip (SoC) performance and productivity. When it comes to verification, it’s not so much the number of transistors that verification engineers worry about; instead, it’s the number of state bits, ie., all of the registers. Each bit can have a value of zero or one, so the problem grows at an exponential level. As such, verification tasks that only required a performance boost in the past may now need now a more productive approach as well.
Addressing intellectual property (IP) block-to-chip and SoC verification challenges, the Incisive 13.2 platform provides an array of new features that further accelerates the verification closure process. Click here for the top 10 features.
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