TSVs Ease Heat In 3D ICs

By Ann Steffora Mutschler
In the evolving discussion of 3D ICs and through silicon via (TSV) technology, a key issue engineering teams are facing today is how to reduce the thermal coefficients between substrates in a stacked die. Simply put, what is the best way to get the heat out of the 2.5 or 3D IC?

The answer, of course, is anything but simple.

“In a 3D system, the heat hierarchy is through the package, through the heat sink, through the bumps, through the adhesives and through the stacked tier layers. If the wafers were thicker, the heat would have a chance to flow out horizontally or vertically and dissipate a bit. As wafers are thinned more and more, the heat dissipation becomes an issue, and if you stack them it gets worse. Within them, thermal flux increases, your peak temperature within the stack increases and since your wafers are thinner, you also have a higher temperature gradient across the thinned wafer,” explained Sesh Ramaswami, senior director at Applied Materials.

The first step in managing thermal issues today is accurately calculating the power and leakage in the design, with leakage now one of the most dominant issues to be addressed.

“The low-dielectric constant materials are actually causing more of a problem because they’ve got lower thermal conductivity. That in itself is not helping with thermal gradients on a die,” said Pete McCrorie, product marketing director at Cadence. Thermal analysis technology employs IR drop power rail calculation to generate instance power in the design, so for each of the instances in a design that power is based on activity information. That is added to the leakage power, which is calculated, and it all gets thrown into a solution where the thermal conductivity of the substrate, interconnects, ball bonds and package is extracted and is solved for thermal at that point.

“When you’re stacking—and it doesn’t matter if it’s a 3D package where the package is a system-in-package or MCM, or a number of die on top of each other—with 3D IC it’s the same thing,” observed Navraj Nandra, senior director of marketing for analog/mixed-signal IP at Synopsys. “The difference between a 3D package is that you do all the signaling off the die, so you have wire bonds going off the substrate and connecting into the other substrate. With a 3D IC, you have on-chip signaling, so you’ve got the communication between the various substrates happening through TSVs, for example.”

So when it comes to all the heat issues, everyone dealing with stacking is basically having the same problems. To combat the heat, engineers try to put the active devices—those devices or transistors doing all of the switching—at the top of the substrate hierarchy where a lot of heat is generated. Looking down further into the stack, IC developers are trying to increase the effective heat transfer coefficient, meaning they are looking for technologies that can shift the heat out very quickly from that substrate.

In terms of the packaging aspect of stacking 3D ICs, one approach is to develop a substrate with better thermal conductivity, but that’s cost-prohibitive for most developers. Intel has done research in this area and released a paper in 2007 with its suggestions for managing thermal issues. http://download.intel.com/design/iio/applnots/31505102.pdf Other approaches leverage familiar techniques that use copper, such as including a copper spreader or copper underfill between the substrates to dissipate the heat.

Then, when it comes to 3D ICs, TSV technology not only gives area, bandwidth and latency benefits, but it also can be used to manage all the thermal problems on a 3D IC by using the signal and power TSVs to dissipate the heat.

Synopsys’ experiments in this area involve taking the concept and introducing more vias or a via array—specifically, a TSV array—to reduce the temperature, Nandra said. “The idea is that if you can understand where the hot spots are going to occur in your design and somehow predict that in your EDA methodology, you can then insert a bunch of TSVs and those will help in the thermal dissipation. The question is how much do they help? We are seeing that they certainly help to reduce the peak temperature and the overall temperature gradients, but they don’t get the minimum temperature down any further.”

Not just for cell phones
Engineers tend to think of low power designs as being the wireless type solutions, but today everyone including the high-performance server developers are looking at lowering the power because of the associated heat and the high energy costs, Cadence’s McCrorie pointed out. “You think about the heating problem of the chip, but then when you try and dissipate the heat from the board and from the environment, that all gets very expensive if you’re generating too much heat.”

Meanwhile, Applied’s Ramaswami believes 3D stacking and TSVs may well pan out in the datacenter. With servers containing multicore CPUs that require lots and lots of data, if DRAMs are used in traditional DIMM approaches there will be several DIMMs on the board. “These DIMMs have a latency factor. They are a little slower because of the wire length, and so on. For the server market the blade would probably have these memory cubes on them [referring to Micron’s Hybrid Memory Cube as an example] with the following advantages: You get more memory per unit volume, which is much closer to the CPU, and because of that the latency goes down and your power dissipation goes down.”

Also, teams building chipsets for datacenters are asking for much lower power consumption for high-speed interfaces than what was typically thought of in the past. “They want something like a 10 or 12Gbps interface, but the power consumption numbers that they are asking for are very similar to what we would have thought in the past would be required by someone in the consumer industry,” Synopsys’ Nandra said. And they don’t always push for the higher performance, opting instead for lower power. “They say, ‘We want the 10Gbps interface, but what we really want is not for you to show us that you can take that 10 to 15Gbps or whatever. We want you to show us your roadmap to get the power consumption of that interface down.’ That’s a different requirement from customers.”

Modeling first
Of course, knowing where to put the TSVs is critical. From the design perspective, the first step is to model the problem with three pieces of information needed: current, resistance and voltage. “Once you’ve modeled the problem then you can think about some kind of automated EDA implementation. The way to think about this is going back to some very basic analogies. In order to do your thermal simulation, you can think of the heat source like a current source, because the current is directly related to heat, and you have an equation to do that,” Nandra said.

Thermal resistance is the other problem that causes heat, which is equivalent to a resistor, and that is equivalent to electrical resistance. Add to this the temperature gradient, which is analogous to the electric potential or voltage. With these pieces of information, a thermal model can be built based on those three parameters, which can then be used with any kind of numerical based simulator to do the thermal equivalent simulation, like SPICE, he explained.

“Then the question is, where do you implement it in the design flow. Fundamentally, the whole idea of 3D ICs is to solve the wiring crisis of interconnects. You’ve tried to solve the RC delay problem by having a vertical interconnect system. But now the next question is, in that EDA model, where do you implement the simulation of the vertical stack of heat?”

Grossly simplified, this is not too terribly complex of a problem in terms of modeling, he admitted. “The complexity is the fact that when you’ve got millions of TSVs in your network that you’re simulating, it all goes into this big matrix in SPICE or whatever numerical simulator you’re using and that becomes a challenge.” As such, there is work to be done with simulators for thermal analysis. More knowledge or heuristics need to be built in to help designers determine where to focus the model of the simulation.

Nandra believes that’s the most interesting aspect of this. “You can take this simple model and apply it blindly to the whole 3D IC, and that’s going to make the matrix that you’re running on the simulator huge. Or you can intelligently think, with some heuristics, ‘Okay, I’ve got 15 areas where this thing is going to get hot, and that’s where I want to apply the model.’ The reason you want to apply the model is because once you understand that the hotspot is occurring in this region, that’s where you want to put your TSV array to reduce the heat in that area. Then you need to know how many vias to put there because there is an area impact. You can do your insertion in that region. In the end, it becomes like a synthesis problem in a way. It’s almost like the way Design Compiler started because there was a way that Design Compiler initially worked out how to size gates based on logical effort and then, over years, the scientists that were working on it figured out some heuristics to make the optimization of that logical effort tuned to what you were trying to synthesize. I think that’s the way that this technology in terms of EDA automation is going to go,” he concluded.

Additional resources:
Examples of TSV technology in production designs today

1. TSV with interposer – Xilinx
2. TSV through memory – Elpida
3. TSVs through a logic chip – Qualcomm but no product out yet. discussed at many conferences.