University of Toronto professor Farid Najm talks about what works best in power management.
Power scheduling, power integrity targets, voltage drop—these are just a few of the power-related challenges you’re no doubt managing in your SoC designs. There aren’t any easy answers, but there are some emerging—and promising—techniques.
Two such techniques, according to University of Toronto Professor Farid Najm, are constraints generation and constraints-based verification. “Power is a first-order concern, like timing,” said Najm, during a recent discussion about power-management techniques during a talk at Cadence’s San Jose headquarters.
Najm, who chairs the university’s Department of Electrical and Computer Engineering, said constraints generation involves the generation of power constraints given voltage-drop bounds. Constraints-based verification, he explained, involves verification of the voltage drop given power constraints.
What’s Causing Power Grid Overdesign?
Najm’s current research is focused on power grid verification and optimization, and on managing the impact of process and environmental variations. He began his talk by sharing some background information on the current power landscape and discussing some common challenges. Today, he said, the power grid topology covers all levels of the metal stack, with some 500 million logic cells and their current sources. In a given chip, many blocks will have their own separate, gated power supply, occupying a certain number of metal layers and connected at the top by the global grid. In every layer, the grid is mostly a regular mesh.
While there are currently various areas of study around power, Najm’s talk centered on power grid verification for voltage integrity and grid reliability, and on power scheduling for turning on/off chip cores or blocks. Power grid verification is needed to check power integrity on a chip. “We need grid verification—early, incrementally, and at signoff. The catch is, you don’t know what the circuit is doing,” noted Najm. Power scheduling accounts for the workload an engineer can run in an SoC without violating power integrity targets. Looking into the future, noted Najm, “We may be able to develop a query engine so that the power controller can ask, ‘Can I bring this up before I shut this down, or will there be a signal integrity problem?’”
In this environment, explained Najm, keeping the power supply regulated is essential to meeting design challenges related to power integrity. And these challenges, noted Najm, are many. Given the hundreds of millions of cells on die and clocks that run at GHz rates, total power is very high. A loss of power integrity has a negative impact on chip performance. Bottom-layer voltage variations affect circuit timing. Voltage overshoot can impact I/O signal noise. Electromigration can be damaging throughout the SoC.
What’s a design engineer to do?
Some engineers are relying on simulation for specific scenarios, while others are using tools and techniques for vectorless verification. However, Najm noted, these options offer limited coverage and optimistic results because both are simulation based.
“The engineering solution from designers is to overdesign,” Najm said. “There’s a lot of pain now on the routing side. Designs take longer to implement because of limited silicon real estate due to overdesign on the grid.”
Benefits of Constraints Generation and Constraints-Based Verification
To address the problems, researchers like Najm are turning to constraints-based verification and constraints generation. Constraints-based verification is based on user-provided current constraints and allows vectorless and early high-level power-grid verification. The approach can be used to find worst-case voltage variations for certain grid nodes and worst-case current variations in every grid branch.
As for grid design problems, said Najm, there aren’t any tools today for early power-grid generation. He noted, “There’s no way to tell how much total current the early grid supports without causing power integrity problems, no way to tell what chip workload patterns are allowed by the candidate grid.”
Constraints generation represents a potential solution. Through this methodology, an engineer can generate circuit current constraints that, if satisfied by the underlying circuitry, would guarantee power grid safety. This approach would:
• Encapsulate useful information about the grid;
• Provide power budgets to drive the design process, allowing rebudgeting or providing early hints for grid redesign or a new floorplan;
• Allow local checks for block compliance with grid safety constraints, without grid simulation, and
• Provide constraints for power scheduling.
Power scheduling, in fact, presents a potential killer app for constraints generation. The methodology could, for example, lead to a way for a chip’s power controller to check whether a candidate combination of blocks is safe to turn on, or if it this would violate grid voltage targets.
“Constraints generation is possible and practical, and is a rich area of study that was previously unexplored,” said Najm. “It provides quality metrics for the power grid and a rigorous approach for early grid design and planning.”