Unraveling The Mysteries At IEDM

In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included 2.5D/3D IC chips, III-V materials, finFETs, and next-generation memories and transistors.

During and after IEDM, the real challenge is to put the various pieces together and figure out where the industry is heading at 10nm and beyond. It can be a real mystery, if not a guessing game. For example, at last year’s IEDM, one hot topic was a next-generation transistor technology called the tunnel field-effect transistor (TFET). Intel even presented a paper on TFET, a sub-threshold slope device that enables low-voltage devices. But at this year’s event, TFETs barely made a peep.

So what happened? Did the industry put the TFET on hold or the back burner? Or are Intel and others quietly developing the TFET? Or is gate-all-around FET the next big thing in the industry?

The answer: Based on numerous signals from IEDM, TFETs, gate-all-around and other next-generation transistor types are being pushed out until perhaps 5nm. The same goes for exotic III-V materials. In addition, silicon-on-insulator (SOI) technology remains promising, but IBM and STMicroelectronics are still the only ones backing it. And 450mm technology is in hibernation, if not dead in the water.

In CMOS, what stood out at this year’s event was fairly apparent—What will happen at the 7nm node? At the event, chipmakers also discussed their current finFETs at 16nm/14nm. The industry also talked about the challenges beyond 7nm, but the real emphasis is 7nm.

So what will 7nm look like? “With a change in materials, finFETs can extend to 7nm,” said Reza Arghavani, a fellow at LAM Research. “We know how to do III-V (for the channel materials), but III-V is a challenge. It’s not within reach in terms of manufacturing yet. For the channel materials, silicon germanium or germanium are within reach.”

But to enable 7nm finFETs, the industry will require a plethora of new technologies. Many of the challenges are obvious—design costs, economics, EUV and multiple patterning. At various panels and sessions, chipmakers also brought up some not-so-obvious challenges—contact resistance, materials, power consumption, interconnects, variability and yield. Others were not even mentioned, such as process control, photomask complexity and the ongoing consolidation in the fab tool industry.

Attending one session or panel at IEDM cannot possibly give a complete picture of the challenges at 7nm and beyond. In fact, one must go to multiple events just to get the pieces of the overall puzzle.

Big trends
On the first official day at IEDM, IBM, Intel and TSMC separately presented the latest details of their respective 16nm/14nm finFETs. The technologies will provide some clues in terms of how the industry will scale from 16nm/14nm to 10nm finFETs. For example, Intel made use of air-gapped interconnects at 14nm.

Getting to 16nm/14nm is a monumental achievement. But going to 10nm and beyond presents some new challenges, namely cost and complexity. “The challenge is financial,” said John Chen, vice president of foundry and technology management at Nvidia, during a panel discussion at IEDM. “It’s the economics.”

Indeed, as the industry scales to smaller feature sizes, fewer companies can afford to design and make chips at each node. And needless to say, fab, process R&D, and design costs are soaring at each node. “Unfortunately, it’s not getting any easier,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel, during the same panel. “The mask count goes up. The complexity goes up. The challenges go up.”

In fact, chipmakers are scrambling to stay on  by reducing the cost-per-transistor by about 29% at each node. But to stay on the curve, chipmakers must cram more transistors and functions on the same chip. “We certainly all struggle with the fact that wafer costs go up as we add more masks, but we achieve an ever better (transistor) density at each generation,” Bohr said. “That’s the main goal. If you can’t deliver a lower cost per transistor, it’s not worth funding that next technology.”

In chip scaling, one of the bigger stumbling blocks is lithography. Chipmakers are begging for extreme ultraviolet (EUV) lithography to reduce costs and complexity. Needless to say, EUV is late and not ready for production. “It’s amazing how long lithographers have been able to extend the use of 193nm wavelength,” Bohr said. “Eventually, we’ll need some replacement for that. EUV is the likely next step. I wish it was here today, but it’s not. As a manufacturing tool, it has a long way to go to meet wafer throughput requirements and tool uptime performance.”

Beside lithography, other tool technologies are under pressure to stay on Moore’s Law. For example, multipatterning places new demands for deposition and etch. There are also new demands for CMP, epi, ion implantation and other tools. “All of these require the upmost precision,” said Randhir Thakur, executive vice president and general manager for the Silicon Systems Group at Applied Materials. “Every part of the (equipment) business is seeing changes, which requires innovation and investment.”

Challenges for 7nm and beyond
Meanwhile, during a separate panel at IEDM, the focus was on issues at 7nm and beyond. “10nm will be kind of similar to 14nm,” said Karim Arabi, vice president of engineering at Qualcomm. “But at 7nm, we see it as another inflection point.”

In fact, finFET transistors will likely extend to 7nm. But at 7nm or sooner, the industry may need to move towards a new channel material to boost the mobilities. In other words, silicon-based channel materials may simply run out of gas. III-V materials are not ready for 7nm. So, the industry is leaning towards silicon germanium or germanium for the PFET and silicon for the NFET. “Silicon germanium and III-V would be the candidates to consider,” Arabi said. “Silicon germanium is a possibility.”

As before, the industry wants EUV for patterning. But if EUV remains delayed, then the industry may require the unthinkable at 7nm—193nm immersion with octuple patterning. “I don’t feel good about octuple patterning,” said Michael Guillorn, a research staff member at IBM, during a question and answer session at the panel. “I would rather use EUV.”

One of the initial needs for EUV is in the back-end-of-the-line (BEOL), which involves the tiny interconnects in chip designs. The industry requires new breakthroughs in the arena and for good reason. Chipmakers face the dreaded RC delay issues starting at 20nm. All told, the industry requires EUV to simplify the patterning schemes in the BEOL, according to Guillorn.

Chipmakers also require new breakthroughs in terms of new materials in the BEOL. For example, the industry is looking at cobalt. Other materials are also in the pipeline to alleviate the RC delay issues.

In addition, the industry is looking beyond 7nm. “We have the finFET,” said Aaron Thean, vice president of logic process technologies and director of the logic device R&D program at Imec. “The fin width today is about 7nm to 8nm. You can get down to a 5nm fin width. But you can’t keep doing this, because you will get mobility degradation.”

So at 5nm, the industry may need to move to a next-generation transistor. As before, there are several options on the table, such as gate-all-around FET, nanowire FET, quantum-well finFET and TFET. “We need a new solution,” Thean said. “You might need a more complicated structure like a gate-all-around. But there is no clear solution going forward right now.”

Needless to say, there are still many unknowns. At 5nm, though, the industry believes Moore’s Law will remain intact. “The projections suggest that at 5nm, you still have a decent shot of having the cost-per transistor going down enough to be interesting,” said Witek Maszara, a distinguished member of the technical staff at GlobalFoundries. “If those innovations do not happen, perhaps 5nm technology could be done alternatively.”

In fact, the other option is to go vertical. Imec, for example, has been developing a vertical nanowire structure. In addition, there is 2.5D/3D stacked die, but that technology is still on the runway. And then, CEA-Leti is pushing monolithic 3D. In this technology, a chipmaker would stack leading-edge transistors on top of each other.

Over time, the industry may take two paths. Chipmakers will not only pursue a traditional chip architecture, but they will also embrace a 3D-like technology. The challenge is to pick the right solutions. Beyond 5nm, there are even more unknowns. It’s unclear if silicon will scale beyond 3nm. Carbon nanotubes, graphene and other exotic 2D technologies sound interesting, but these materials all have difficult challenges.

All told, scaling will keep the industry busy for the foreseeable future. But clearly, it will be an expensive and difficult task to stay on Moore’s Law.