Virtual Modeling With Aldec And Imperas

How to simulate and debug virtual models of processors, memories and peripherals without slowing down the rest of the emulation process.

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Virtual platforms play a significant role in system level development, but require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and Software design teams are now able to simulate and debug virtual models of processors, memories and peripherals while the rest of the system resides in the emulator board running at MHz clock speeds.

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