Alternative patterning technology makes incremental gains, but the big money is still behind EUV.
Directed self-assembly (DSA) was until recently a rising star in the next-generation lithography (NGL) landscape, but the technology has recently lost some of its luster, if not its momentum.
So what happened? Nearly five years ago, an obscure patterning technology called DSA burst onto the scene and began to generate momentum in the industry.
At about that time, GlobalFoundries, Intel, Micron, Samsung and TSMC began to explore DSA in the lab, and for good reason. DSA, an alternative patterning scheme based on block copolymers, promised to solve many of the cost and complexity woes in advanced lithography.
Today, chipmakers continue to explore DSA, but the technology appears to be losing some steam. As it turns out, DSA is taking longer than expected to develop and is still not in mass production in semiconductor fabs.
“It is not moving into production as fast as I had hoped,” said Ralph Dammel, chief technology officer at EMD Performance Materials, a supplier of DSA materials and other products, in a recent interview. “I am confident it will come in at some point.”
The original projections were all over the map for DSA. It was supposed to move into the logic production flow anywhere from the 14nm to 7nm nodes. And the technology was targeted for DRAM production sooner than later.
DSA may show up in niche-oriented applications in the near term. But the technology isn’t expected to move into high-volume manufacturing for mainstream IC applications for another two to four years, according to a survey at the recent DSA Symposium, a major event held by the chief backers of the technology.
The industry is still wrestling with the same old problems with DSA. The biggest problem is defectivity, followed in order by pattern roughness/uniformity, placement accuracy, and material quality control, according to the DSA Symposium survey. Integrating DSA into a fab flow and designing chips around the technology also remains problematic.
At the same time, the industry has thrown its weight behind more traditional patterning schemes, a move that has pushed out the insertion point of DSA. In addition, there are signs that many of the resources and dollars have shifted from DSA to extreme ultraviolet (EUV) lithography. Given the billions of dollars spent on EUV thus far, the priority among many chipmakers is to get EUV to work first.
What is DSA?
Still, there is a glimmer of hope for DSA. This technology entered the picture in 2007, when it landed on the old International Technology Roadmap for Semiconductors (ITRS) as a potential and futuristic lithographic solution.
DSA is not a hardware technology. It’s a chemical-based complementary solution based on block copolymer materials. In the DSA process, the copolymers undergo a separation phase. Then, when used in conjunction with a pre-pattern that directs the orientation of the materials, the copolymers self-assemble into a tiny pattern. All told, DSA reduces the pitch of the final printed structure.
Today’s DSA is based on poly (MMA-co-styrene), or PS-b-PMMA, materials. PS-b-PMMA materials don’t scale beyond 11nm. So, the industry is working on DSA materials based on high chi formulas that scale beyond 11nm, but they are still in R&D.
In SADP/SAQP, the process flow involves traditional steps like lithography, deposition and etch. In DSA, though, the key process steps are conducted in a wafer track system, not in a lithography scanner. DSA, however, can work in conjunction with today’s optical lithography tools or even EUV.
There are two types of DSA flows—graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide structure is spin-coated, rinsed and spin-coated again with copolymers using a track system. In chemical epitaxy, self-assembly is guided by lithographic-determined chemical patterns.
In the right setting, DSA can automatically pattern lines and spaces, contact holes, vias and other structures in both advanced memory and logic.
For that reason, DSA looked promising. About three or so years ago, DSA was one of the many lithographic contenders at 10nm and 7nm. At the time, chipmakers faced several challenges. EUV wasn’t ready, while immersion/multi-patterning looked complex and expensive.
As it turned out, multi-patterning gained steam. In fact, chipmakers have extended immersion/multi-patterning to 10nm and 7nm. EUV missed the window at 10nm and its status remains unclear for 7nm.
And in many respects, DSA was pushed aside. That hasn’t stopped progress completely, though. The industry has improved the defect levels for DSA over the years, although this and other issues remain problematic. “There is still a lot of focus on DSA for certain applications,” said Rich Wise, technical managing director at Lam Research. “There are thermodynamic challenges. Line-edge roughness is also a challenge.”
Line-edge roughness (LER) is problematic in lithography. It is defined as a deviation of a feature edge from an ideal shape, according to Chris Mack, a lithography expert.
Another claim to fame for DSA is that it can make tiny contact holes. But in DSA, the challenge is to control them in the desired arrangements. “Therefore, placement accuracy would then become an issue,” said Aki Fujimura, chief executive of D2S.
Still, despite the challenges, the DSA community remains upbeat. “DSA has made good progress to understand what it can do and understand where the limitations might be,” said Greg McIntyre, department director for the Advanced Patterning Unit at IMEC. “We are still fairly confident we can find a place for it in the industry.”
For some time, Imec has operated a 300mm DSA pilot line. In addition, Albany Nanotech and Leti are working on DSA. And chipmakers continue to evaluate it.
Looking for an app
So what are the current and future applications for DSA? Or, for that matter, will the industry ever use it?
For the foreseeable future, DSA isn’t ready for insertion in the patterning flow for mainstream logic and memory. In the near term, though, DSA may show up in more niche-oriented applications. “We are going to start to see more DSA, but not necessarily for conventional patterning,” said David Fried, chief technology officer at Coventor.
“The first time we see DSA will be in pattern healing or pattern repair. Again, that will be an incremental improvement. It will be an evolutionary addition to the patterning scheme,” Fried said. “It will not be a groundbreaking or an earth-shattering change, especially in logic. We may see DSA for memory, because the designs are so much more regular. But we are still pretty far away from high-volume manufacturing applications for DSA.”
Indeed, for logic, DSA faces an uphill battle.
“There are particular challenges for logic,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries. “To get the types of shrinks we need, we need to have more than a single pitch. Getting that for line/space patterns with DSA is problematic today. Again, when you try to use it for contact and via layers, it’s getting the non-periodic structures that you get in random logic. There also has to be a lot more work done on the lithography design co-optimization side to make this work. There needs to be more work that takes place in terms of creating a low defect process on the wafer. There are still a lot of substantial issues here.”
So for logic, the DSA community still has a lot of work to do. DSA might never be ready for logic, although there is hope for it in DRAM. “Memory is probably going to be the first insertion point for DSA, because of the redundancy in these devices,” said Uday Mitra, vice president and head of strategy and marketing for the Etch Business Unit and Patterning Module at Applied Materials. “This could be DRAMs or even some of the newer memories.”
In fact, DRAM makers are looking for a new lithographic solution for good reason. It’s becoming difficult to scale the DRAM beyond 20nm. The traditional one-transistor, one-capacitor (1T1C) cell structure in the DRAM is running out of steam.
Today, vendors are scaling the DRAM from 20nm to the 1xnm node regime. The DRAM is expected to scale three iterations in the 1xnm regime, which is referred to as 1xnm, 1ynm and 1znm.
To scale the DRAM at 1xnm and beyond, DRAM vendors are currently using 193nm immersion and SADP/SAQP. DSA and EUV are possible solutions as well.
At a recent event, Samsung presented a paper that described how the company plans to scale today’s planar DRAMs down to 20nm and beyond. For this, Samsung developed a new cell layout scheme, dubbed the honeycomb structure (HCS).
With HCS, the company developed a flow using today’s 193nm immersion and SADP. “For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet lithography,” said J.M. Park, a principal engineer at Samsung.
But there are several challenges to extend immersion/multi-patterning for advanced DRAMs. “Patterning 1xnm half-pitches and contacts without EUV will be surely painful,” said Chang Yeol Lee, a research fellow at SK Hynix. “It requires long and tedious work to hold CD uniformity and to align the quality.”
For this reason, DRAM makers are still looking at EUV. But as before, EUV is still not ready for prime time. “EUV hits the right cost point,” said Naga Chandrasekaran, vice president of process R&D at Micron Technology, at a recent event. “It gives you a significant benefit. The key question is, ‘Do the economics work?’”
Another option is DSA. “(DSA) is more suitable, in my opinion, for line/space patterning,” Chandrasekaran said. “And there, we are still struggling with line-edge roughness. Line-edge roughness clearly translates back into your CDU. Quad patterning is still better in terms of line-edge roughness.”
Still, the DSA community isn’t throwing in the towel. For example, Imec is working on a DSA process for future DRAMs. The process, dubbed the Chips Flow, is based on a chemical epitaxy scheme. The flow enables hexagonal cell layout patterns, which resembles Samsung’s HCS scheme.
“The memory world is taking a hard look at Chips Flow,” Imec’s McIntyre said. “It’s a chemo-epitaxial pillar formation for the use of creating capacitors in DRAM types of layouts. This could be a potential cost savings alternative.”
Long term, DSA could find a place in more mainstream applications, if the industry can overcome some major challenges.
The key is to develop the next-generation, high-chi materials, which will scale beyond 11nm. But integrating these exotic high-chi materials in the fab presents some challenges.
To solve this problem, Imec, TOK and the University of Chicago are developing a DSA technology that could extend today’s PS-b-PMMA beyond 11nm. Researchers have added an ionic liquid to these materials.
“Basically, they create a stronger entity that turns into a high chi,” McIntyre said. “So, you can do sub-10nm half-pitch imaging with the added benefit of having the same materials that we usually work with. It’s still very much in the research phase and feasibility study stage. The truth is we don’t need those dimensions at this point quite yet. That’s still a couple of years away.”