Where Is Next-Gen Lithography?

Experts at the table, part 1: Ramp up time still in question. Remaining issues include power sources, pellicles, thinner wires, edge placement and cost.


Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at IMEC; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Uday Mitra, vice president and head of strategy and marketing for the Etch Business Unit and Patterning Module at Applied Materials; Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation.

SE: Briefly, from your vantage point, what are the biggest challenges that we face in the industry today?

Fujimura: Part of it is cost. Cost per die for the end user is one thing. In the mask industry, we have to do more and more difficult things. And we have to do it cheaper. That’s really getting difficult.

Hayashi: It’s the same thing. Customers need to release many devices in a short period. They are under pressure, of course, with mask-set costs and short turnaround times. Those are two things we are fighting. Also, the device demand is changing a little with the IoT and those kinds of things.

McIntyre: There is no one thing that is the biggest challenge. Clearly, there are many, many challenges happening in parallel. Collectively, the challenge is to collaborate and understand how things are working and progressing in adjacent areas. We also need to understand how we can best overlap our expertise and interests to solve problems together.

Mitra: Cost and edge placement error are probably the biggest challenges. You have design and litho. On the process side, you have a lot of different materials. You also have a lot of different schemes in terms of using these materials. The question is how do you deposit and etch them selectively. Those are the kind of tricks and innovations we need.

Levinson: I see a couple of challenges. From the pattern materials side, we are really starting to hit the point where molecular scale has to be taken into consideration. Some people have put some thought to it. But this is one where a great deal more thought needs to be put into that. The other one that worries me considerably is electrical resistance. Over time, we had to move from aluminum to better conductivity copper. And there just isn’t another element out there that can give us a similar boost. So a great deal of work is going to have to be done to try and figure out how to get good conductivity with very, very narrow wires. Again, that’s something that I think there has been very little work done to date. It’s just enough to know that we have a problem. Much more has to be done to start turning the corner and working towards long-term solutions.

SE: Now, I’d like to talk about the different lithography technologies, such as EUV, DSA, multi-beam, and 193nm immersion and multi-patterning. Let’s start with extreme ultraviolet (EUV) lithography. What’s the status of EUV? Will we see it in mass production at 7nm or 5nm?

Levinson: First, it’s a little misleading to talk about the nodes, because each company probably has a different meaning in terms of what pitches we are talking about by nodes. But it’s fair to say that EUV technology has reached a certain state of maturity. If you listen to recent talks by Intel, TSMC and Samsung, along with GlobalFoundries, we all share the view that things are headed to the point where in two to three years EUV will have capability for use at the manufacturing level, certainly for some contact and via-type layers. Typically, we now need triple patterning and quadruple patterning.

McIntyre: A significant ramp in the source power, and having tools in the industry that people can actually start development with, have created a surge in the development for EUV. All of the other aspects of technology need to fall in place, such as the resist materials. There has been progress in chemically amplified resists, but there has also been a strong surge in alternate materials that have been developed over the last year. We’ve seen some pretty good progress with these. Also, on the mask side, we have a pellicle. A year and a half ago, that was unthinkable. But right now, you see full-field prototypes and concepts of materials that could potentially handle the high power levels that we will eventually get into high-volume manufacturing.

SE: Is the EUV mask infrastructure ready today?

Hayashi: We had a five-year project in Japan to develop the infrastructure for the EUV mask inspection area. So EUV mask blank inspection is ready. But we still need a pattern mask inspection capability for EUV. Specifically, for the pellicle, we need an actinic-type inspection system. So that’s the key for the next node. Also, the progress with EUVL should be evaluated not compared with last year. It should be compared to the current target, and the target is moving. So if it’s delayed another year, the target is becoming more difficult.

Fujimura: EUV does come with specific issues. Regarding the mask itself, it’s a reflective mask. It comes with its own OPC-type issues. The characteristics of the exposures are different on EUV masks as compared to ArF masks. What’s there is similar, but the degree of that is much more severe in EUV. There are several things in the infrastructure, of course. There are pellicle issues. There is no actinic inspection right now. It’s a matter of funding regarding this issue. Until the EUV lithography side is ready and imminent, the degree of investment on the mask side and other parts of it is not going to be as robust. I also see it from another side. By observing what the infrastructure side is doing and how they are investing, you can tell what the world is thinking regarding the reality of EUV and how far away it is. By looking at it that way, it looks like it’s getting closer. So everybody thinks EUV is getting closer.

SE: Like optical masks, EUV masks must be inspected. Today, to do pattern mask inspection for EUV, there are only two solutions available—optical and e-beam inspection. These technologies have some drawbacks and resolution limits. Do we need actinic inspection for EUV masks?

Fujimura: It will require industry funding.

McIntyre: Actinic inspection doesn’t appear as though it’s going to be a showstopper to enable the insertion of EUV. People will likely use EUV without it. But clearly, it’s a cost-of-ownership issue going forward.

Fujimura: There is another way of looking at it. With optical and e-beam inspection, you can’t inspect the mask through the pellicle. You have to take it off and put it back on. What I detect is that people are extremely skeptical about removing the pellicle and replacing it. And you also have to clean it.

SE: What about EUV pellicles? Do we need them or not?

Hayashi: Regarding the initial insertion point for EUV, we may not use the pellicle. Certainly, in memory devices, this is possible because they have redundancy. For logic, they may need a pellicle. In that case, we need to manage the removal of the pellicle with the existing inspection systems. But still, there is kind of a risk.

Levinson: The real concern for me is pellicle breakage. When you have the light being absorbed in a very narrow band on the pellicle, you get a very large temperature gradient. The stress could cause the very thin and fragile membrane to rupture. That’s the real concern. Everyone understands this is an issue. Bright minds are working on it. And we just have to see if we can find solutions.

SE: Today, ASML’s EUV tools are equipped with an 80-watt source, enabling a throughput of 75 wafers an hour. But the industry wants a 250-watt source before they put EUV into mass production. How confident are you we will get to 250 watts by this year or next?

McIntyre: 80-watt sources are in the field, 125-watt sources are in the process of shipping. We should see that early this year. To ramp from 80 watts to 250 watts in a matter of 10 months is a tall order. Demonstrating 250 watts in an ASML factory is certainly likely. But it takes time to roll out those solutions, make them robust, and bring them into the field. So for a 250-watt source, the end of the year is quite challenging. Next year might be a more reasonable target.

SE: When EUV moves into production, chipmakers will likely take a complementary approach in the fab. 193nm immersion will handle some layers and EUV will do others. How will this work and what are the challenges?

Mitra: The industry is headed toward doing grated line/space with SADP or SAQP using immersion. Then, you have EUV to do the contacts and vias. EUV would likely do the cuts as well. That’s one part where EUV would come in. The reason for doing the cuts with EUV is it might eliminate some multi-patterning immersion steps. This assumes EUV is capable of high-volume manufacturing. And at the same time, it also must make economic sense to do that.

McIntyre: At some point, you will start to see EUV multi-patterning pop up. If you use dimensions of what we call the ideal N5 or Imec’s N5 node, which is about a 24nm metal pitch, you might perhaps have to do two exposures for the vias. Maybe even one or two for the cuts. And then, if you want to get fins or some kind of patterns for the 20nm-like pitch, you are looking at self-aligned octuple patterning, or SAOP, with immersion. The other solution is EUV/SADP. So, we will play all of the same tricks as we did in immersion.

Mitra: You still have the edge placement error problem. EUV could certainly reduce it, but it’s still a huge challenge. Cost will be a major challenge in all aspects.

Related Stories
7nm Lithography Choices
EUV: Cost Killer Or Savior?
Is EUV Making Progress?
Gaps Remain For EUV Masks
Resist Sensitivity, Source Power, And EUV Throughput

  • memister

    You can already see the disconnect on pellicle and actinic inspection. That’s another reason it’s not moving forward.

  • Anonymous

    It is an interesting group we have here. Is Mr. McIntyre the only one with an actual EUV machine? His comments standout above the rest. I know it’s hard to get them to talk but I sure would like to know what Intel, Samsung, and TSMC think about these things as they will surely be the ones actually making these decisions.

    • memister

      Globalfoundries (Levinson) has an EUV tool they have access to at Albany. IMEC’s EUV program is a large source of funding so it is common to hear promotions of EUV results from them.

  • Mark LaPedus

    Hi Anonymous, Our panel here strictly explored the issues with EUV (EUV tools, masks, inspection, etc.). For more information, please go to this article: 7nm Lithography Choices http://semiengineering.com/7nm-lithography-choices/ As this article states, Intel and Samsung hope to use EUV at 7nm–if EUV is ready. As reported, Intel will use EUV if it can replace 3 immersion cut masks. If it can’t, EUV will slip to 5nm. TSMC will likely use EUV at 5nm. FYI. GF/IBM have a long history with EUV. I believe GF is working with an EUV tool, which is installed at Albany Nanotech.