As device complexity grows, so does the momentum of IP subsystems.
At the recently concluded DAC 2016 conference in Austin, Texas, I had the opportunity to participate in a tutorial on IP Subsystems on Wednesday the 8th. Also participating were Marco Brambilla, Director of Engineering at Synapse Design and Drew Wingard, CTO at Sonics.
The reality today is that device complexity in many applications has risen to levels that require increasing amounts of discrete IP, and the effort to integrate these blocks is a direct contributor to rising design costs. The SoC market has started using IP subsystems in place of using many discrete IP blocks to create the different system-level functions required by contemporary applications. This is being done to reduce the level of effort needed to create these system-level functions while at the same time increasing performance and functionality.
This design approach has been practiced internally at many of the larger semiconductor companies for at least the last ten years and has now entered the third-party IP market as a viable design alternative. Semico has identified 12 different categories of IP subsystem and at least 16 vendors, some with multiple products. The momentum is building as more designers reach the point where this approach makes sense to apply to their silicon solutions.
Marco Brambilla spoke about his experience at Synapse Design in implementing an internally designed IP subsystem aimed at IoT applications. He noted that aggregating multiple blocks from multiple vendors to create the needed system-level functionality can be challenging, especially managing the different license agreements for each block. In addition, performing the verification on all the individual blocks is time consuming and may need to be run many times before completion. Acquiring an IP subsystem of the right functionality can reduce much of this effort and lets the designer concentrate on other areas of the design.
Drew Wingard spoke about a new approach Sonics is taking in creating a ‘distributed’ subsystem that addresses power management issues down to the state-machine level. This provides greater granularity to the designer in managing power consumption in the silicon. The subsystem is distributed in the sense that it does not reside in one contiguous block in the silicon but is emplaced around the part, touching all the areas where power management is desirable and necessary. This represents a new class of IP subsystem in the market in response to the need to distribute functionality around the silicon while increasing performance at the same time.
During the question and answer session at the end of the presentations, the question of EDA tools to support IP subsystem integration came up. As more designers employ third-party IP subsystems, the EDA companies are responding with the first tools aimed at aiding the designer in the integration effort. EDA tools focused on the writing of the software to be executed by the silicon are also starting to enter the market. This could be especially important to the SoC design landscape since the IP subsystem concept allows for the software resident on each subsystem to be written in parallel instead of serially. At the 28nm node software design costs exceeded silicon design costs and have continued to accelerate at each new node. A method to rein in the growth in software design costs would be very welcome by silicon designers today.
The IP subsystem concept involves a “divide and conquer” design strategy that enables designers to increase integration and meet rising customer expectations of performance and functionality. Semico Research has a new report, “The IP Subsystem Market: An Evolving Landscape,” which examines this market in detail. Different SoC types are aimed at different applications, and the report details the average number of discrete IP blocks per Basic, Value Multicore, and Advanced Performance Multicore SoC. The fastest growing segment is Advanced Performance Multicore with a CAGR of 15% from 2015 to 2020. The report provides information about the IP subsystem concept, products and vendors in the market. It also provides an assessment of the issues facing designers and potential solutions for those issues.