Central fins can be up to 50% hotter than other fins, causing inconsistent threshold behavior and reliability problems.
New transistor designs and new materials don’t appear out of thin air. Their adoption always is driven by the limitations of the incumbent technology.
Silicon germanium and other compound semiconductors are interesting because they promise superior carrier mobility relative to silicon. FinFET transistor designs help minimize short channel effects, a critical limitation of planar MOSFETs. But there’s no such thing as a free lunch. These innovations also bring limitations and tradeoffs of their own.
For example, the vertical fins of a finFET transistor are wrapped in an oxide layer. Depending on the design, the physical connection between the fins and the silicon bulk is either very narrow or non-existent. Yet they operate at relatively high voltages, thereby generating high current densities and correspondingly high operating temperatures. This combination of increasing operating temperatures and poor heat dissipation can lead to localized thermal effects, commonly known as self-heating.
Hot spots in integrated circuits are nothing new. Designers are used to managing the heat dissipation needs of heavily used parts of the circuit. But self-heating is much more localized. Rather than affecting certain circuit blocks, it affects individual fins within a single finFET.
Specifically, heat is generated by current flowing through the channel, and dissipates through the contacts and by whatever thermal coupling to the bulk semiconductor exists. In a multi-fin structure, the central fins tend to be warmer because they are further away from the contacts. In fact, in work reported at December’s IEEE Electron Device Meeting, S. H. Shin and colleagues at the Korea Institute of Science and Technology (KIST) found that central fins were 30% to 50% warmer. Such extreme variations within the transistor can cause inconsistent threshold behavior and accelerate reliability failures.
Self-heating and reliability
In highly scaled planar transistor designs, bias temperature instability is the most severe threat to reliability. As previously discussed, BTI occurs when trapped carriers cause a threshold voltage shift. Because the number of traps in a single nanometer-scale transistor is quite small, they must be viewed as discrete locations distributed according to Poisson statistics, rather as an average distribution that can be applied to all transistors equally. Combined with self-heating effects, BTI exacerbates Vt mismatch within a circuit due to doping fluctuations.
Fortunately, there is some evidence that the fully-depleted channels typical of finFET devices help minimize BTI by reducing doping variability. SiGe devices also appear to be less prone to BTI, as a passivation layer decouples the energy levels of channel holes from those of dielectric defects. On the other hand, SiGe channels appear to be more susceptible to hot carrier-induced degradation. Hot carrier injection occurs when high electric fields drive carriers into or through the gate dielectric. It is made worse in finFETs due to their small dimensions and the larger electron capture cross-section of “wraparound” gate architectures. HCI is especially problematic in SiGe because the reduced band gap lowers the barrier to injected carriers. In fact, researchers at IBM found that hot carrier injection appears to be the dominant degradation mechanism in SiGe finFETs at low and moderate gate bias, making hot carrier-induced dielectric punch-through a potential limiting factor for the lifetimes of those devices.
Both HCI and BTI involve carrier trapping/de-trapping processes. Applying a bias populates the trap locations with carriers; removing it allows the carriers to return to the ground state, restoring the transistor’s original behavior. As a result, ultimate reliability depends on the circuit’s duty cycle. The rapid switching of modern CMOS circuits is an advantage, in that it allows more recovery time than traditional DC stress models assume.
A third important failure mechanism, time-dependent dielectric breakdown, is a bit different. TDDB doesn’t depend on Vt alone, but on the electric field and trap density in the gate oxide. S. Mei of Singapore University of Technology and Design, with colleagues at Imec, observed “dielectric breakdown-induced epitaxy,” in which thermal and electromigration of silicon from the channel into the oxide caused physical thinning of the dielectric, eventually resulting in a short.
Self-heating increases the migration rate. Zero-bias TDDB failures can occur in central fins. In both central and edge fins, however, migration was localized at the bottom corners.
Thermally aware transistor design
Self-heating, then, can have a significant impact on finFET reliability. So what can be done? Or is it an inherent characteristic of finFET transistors, forcing a tradeoff between temperature management and electrostatics? On this front, the KIST group offered a bit of good news. Their modeling of floating body transistors, independent of materials or transistor design, found that self-heating behavior is most affected by the heat dissipation characteristics of the substrate and buried oxide. The electrostatic behavior of the transistor is most affected by the channel and the gate dielectric. As a result, self-heating and electrostatics can be decoupled and optimized separately. For example, these researchers were able to reduce channel temperature by 50% to 70% through use of a buried Al2O3 layer on a SiC substrate.
While self-heating does not appear to overwhelm the electrostatic benefits of finFET designs, it is clear that thermal effects will require careful attention as the industry incorporates ever more exotic device materials and structures. Researchers at Imec offered some useful suggestions based on their work with nanowire devices.
Nanowires and the future of self-heating
For example, it’s important to remember that thermal conductivity and electrical mobility are not the same. SiGe has better carrier mobility than silicon, but germanium’s distortion of the silicon lattice increases phonon scattering and degrades heat transfer. Similarly, surface preparation matters. For example, many nanowire integration schemes use etching to reduce wire width. Current flows in the wire bulk and is not affected, but surface characteristics affect the thermal coupling between the wires, dielectrics, and the wafer bulk.
Finally, it’s important to consider parasitic currents and the heat they generate, as well. For example, air-gap spacers intended to reduce the capacitance between the gate and the source and drain may be counter-productive. Degraded performance due to reduced heat dissipation may offset the benefits of reduced capacitance.
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