Sharing IC verification challenges and solutions.
All too often we get caught up in our own work and our own issues, thinking no one else could possibly be having as much trouble as we are. The reality is that many, if not most, of the problems and challenges in IC verification are not unique to one design, one team, or one person. The natural reluctance of people to admit they are struggling with some aspect of their job often keeps them from finding out that they are not alone.
As an EDA vendor, support is a critical service, and our engineers take pride in helping our customers solve difficult issues. However, we often have the opportunity, through support requests and problem reports, to identify common topics and tasks where many designers may need additional guidance or instruction. After evaluating ideas for making our engineers’ expertise more accessible to more people more quickly, we initiated our Calibre How-To video library – short, targeted videos that illustrate a specific verification task. As these videos quickly became highly popular, we found that, rather than having to identify new topics ourselves, we were now receiving requests directly from the viewers. In fact, to streamline the process, we even created a direct submission point. Designers can use this site to review suggestions already submitted, and to submit their own ideas and requests.
For example, one area that many designers contend with is layout vs. schematic (LVS) debugging. LVS debugging is often a tedious and time-consuming process, requiring many iterations and cross-functional interactions before a designer team converges to a LVS-clean design. In addition, many errors can manifest themselves in unusual ways, causing designers to experience a lot of frustration and waste a lot of time trying to identify and fix them. Designers often find themselves in need of expert guidance to comprehend complex LVS issues and determine the most appropriate way to fix errors without compromising the performance quality of their design, especially when they are under pressure to meet the ever-tightening tapeout deadlines of today’s IC market.
Of course, there are many areas of specialty within the broad concept of LVS debugging, so our challenge is to analyze the requests and suggestions we receive, and identify and isolate common problematic tasks for both general and more targeted audiences. Evaluating the various requests associated with LVS debugging allowed us to target four high-priority topics that most LVS engineers encounter: troubleshooting short circuits, debugging soft connections, cross-probing nets and highlighting nets.
Troubleshooting short circuits proved to be a popular topic, so much so that we ended up creating two videos for it, each focusing on one specific aspect of the process. How To Debug multiple shorts on the same net demonstrates how to test proposed fixes to shorts in the layout and potentially avoid multiple runs. How To Debug non-texted shorts using Calibre RVE walks the user through valuable techniques for highlighting devices in both the schematic and layout, and describes a method of thinking about non-texted shorts that enables the user to work through them in a logical way.
Soft connections and soft check output refer to connectivity that may be accidental, or not robust enough to qualify as good connectivity. These types of issues are commonly associated with wells or substrate connections, and can be difficult to work with, due to their large number of connections and broad scope. How To Debug “soft check” warnings with Calibre RVE demonstrates specialized highlighting techniques, and shares some ideas for understanding the graphical output to help find the root cause of the problem.
Cross-probing and highlighting techniques are valuable in many LVS debug situations. How To Cross-Probe nets in the design environment using Calibre RVE demonstrates the selection of nets in the schematic window to highlight the corresponding nets in the layout. If a designer knows the name of a net, and just wants to see where it is in the layout, the How To Highlight a net by name using Calibre LVS RVE video displays an easy process. It also shows the designer how simple it can be to separately highlight just the portions of that net for specific layers of interest, such as metal or poly. This process can streamline examination of nets that may be difficult to see or find in a complex layout, and help designers confidently see exactly where they are, and exactly how they are formed.
Of course, Mentor support engineers sometimes deal with very difficult LVS debug issues that are unlikely to be seen by the majority of LVS users. Even specialized LVS engineers can find themselves caught up in the trickiest of debug conditions at times. For example, How To Create annotated GDSII files for advanced LVS troubleshooting explains to these designers how the Calibre Query Server can be used to create a highly-specialized graphical database they can then explore to see how Calibre interpreted and processed the hierarchical layout database. As an adjunct, How To Use annotated GDSII (AGDS) files in advanced LVS debug presents a few techniques to give designers additional ways to use this special graphical database.
As you can see from these examples, if you’re encountering difficulty, then it’s extremely likely many other people are too, no matter what your level of expertise or experience. Rather than keeping your struggles a secret, sharing your roadblocks, and your ideas for what you might need to solve a problem, can now lead to creation of directed content that will be ready for you (and your teammates) the next time that problem occurs. In fact, your suggestions, along with suggestions from many others, may even lead to videos that help designers (including yourself!) avoid creating a problem that needs to be fixed. That’s the best type of problem resolution there is. Think of it as the Calibre How-To-Video version of paying it forward.