May 2009 - Page 2 of 2 - Semiconductor Engineering

Lines Blur Between Processor And Microcontroller

By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Big changes are happening in the microcontroller market. That statement alone should give pause for most design engineers and raise their level of skepticism. In the past, microcontrollers were a steady business but not exactly an interesting one. That was before the big push toward “green” and the 65nm process node. And it was before vendors began adding logic and more fun... » read more

The Gleaning Power of Piezo

By Brian Fuller - 13 May, 2009 - Comments: 0

By Brian Fuller The inventor and green-tech missionary Trevor Baylis walked 100 miles across an African desert nearly 10 years ago to prove piezoelectric technology could power a cell phone. It was an interesting story that quickly faded from memory, as the technology was deemed clever but impractical. Enter Elizabeth Redmond and Andrew Katz, who have taken Baylis’ inspiration and piezo’s... » read more

Lower Power, Bigger Problems

By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Low power used to be an afterthought in semiconductor design, and it almost was never a consideration in verification or manufacturability. But at each new process node, the number of power considerations goes up as the line widths go down. To begin with, there are two basic types of power. The first is dynamic, which has been a consideration ever since batteries were added int... » read more

Less Room For Error

By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Say goodbye to fat design margins in advanced SoCs. The commonly used method of adding extra performance or area into semiconductors to overcome variability in manufacturing processes or timing closure issues has begun to create problems of its own. While there was plenty of slack available at 90nm, adding margins at 45nm and 32nm disrupts performance or eats into an increasing... » read more

Home Sweet (Power-Hogging) Home?

By Brian Fuller - 13 May, 2009 - Comments: 0

By Brian Fuller Numbers, history and technology are on a collision course inside your home. Consider the numbers: The big picture points to an even bigger opportunity for smart system design that can reduce power in and out of the chip. Since 1982, growth in peak demand for electricity has exceeded transmission growth by almost 25% every year. Yet spending on research and development �... » read more

How Many Power Islands Is Too Many?

By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Power domains, also known as power islands, have become to design engineers what multiple cores are to processor architects. They can serve a purpose, namely reducing static current leakage and saving battery life. But they also can add so much complexity that they can make it almost impossible to get a new chip out the door. Just as there has been talk of hundreds of cores, th... » read more

Tesla: The Ultimate Low-Power Design

By Ed Sperling - 13 May, 2009 - Comments: 0

When your battery pack alone costs $30,000 and you get 200 miles per charge, you've got to be looking for ways to save power. The Tesla roadster is crammed with parts from many Silicon Valley companies, all designed to draw as little power as possible. But there's still much more work to be done. [youtube vid=qdGLvJzBUYI] » read more

VMM vs. OVM Becomes More Important

By Ed Sperling - 07 May, 2009 - Comments: 0

For all the talk about VMM vs. OVM and how it doesn’t matter…well, apparently it does. It’s not that one verification environment is so much better than the other. That’s like saying one religion is better than another. People kill each other over those kinds of statements. And the truth is, there are plenty of people who will argue for and against each side. Strangely, when... » read more

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