August 2009 - Page 2 of 2 - Semiconductor Engineering

Following The WLAN Alphabet To Lower Power

By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Cheryl Ajluni The quest for low power in electronic devices is one that shows no sign of abating any time soon. Pressure for it comes from many different sources, such as the continual drive to pack more functionality into ever smaller, mobile electronic devices. To try and maintain a decent battery life for today’s power-hungry “road-warriors,” engineers have to reduce power con... » read more

An Inside Look At Transaction-Level Power Modeling

By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Ann Steffora Mutschler With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial architectural design. The only way to do that is to model power consumption at the transaction level. While power is typically estimated after RTL synthesis, the better a... » read more

Mythbusters: Moore’s Law, Low Power And The Future Of Chip Design

By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Ed Sperling Contrary to popular belief, Moore’s Law is not in serious trouble. Nor will active power in most devices be reduced to the millivolt or microvolt level anytime in the near future. And chip design will not disappear, be relegated to the push of a button or move offshore from one low-cost wage location to the next until ultimately it gets to a place where no one is paid a salary... » read more

Experts At The Table: Building A Better Mousetrap

By Ed Sperling - 20 Aug, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

Dynamic Simulation In Power Management Verification

By Bhanu Kapoor - 20 Aug, 2009 - Comments: 0

In the previous blog article, we took a look at some of the main power management verification issues encountered in low-power designs. Typical power management verification strategy requires a combination of structural rule-checking, power-aware simulation, and formal validation to address these issues. One question that comes up very frequently is that of how much more simulation is neede... » read more

Handcrafted Designs

By Ed Sperling - 20 Aug, 2009 - Comments: 0

Ludo Deferm, VP of business development at IMEC, the Belgian research house, talks about changes ahead at future process nodes. [youtube vid=8b6O52qY0bs] » read more

When It Comes To Intellectual Property, Size Matters

By Various Writers - 19 Aug, 2009 - Comments: 0

By Geoffrey James Intellectual property was once seen as the new growth market for EDA. Dozens of firms – large and small – jumped on the IP bandwagon, attracted to the “build once, sell many times” business model. “As late as 2004, the industry was still thinking that as much as 90% of SoCs would be reused IP,” said EDA consultant Gary Smith. The IP segment, however, hasn�... » read more

Dropping The Voltage: Now What?

By Ed Sperling - 16 Aug, 2009 - Comments: 0

By Ed Sperling Ratcheting down the voltage in an SoC design seems like the simplest way to reduce power consumption, but it doesn’t always work out that way. In fact, reducing voltage can have some rather strange and unexpected effects at all levels of chip design, including testing and debugging. The problem is that not all parts of the chip work the same way without a minimum am... » read more

Experts At The Table: ESL And Low Power

By Ed Sperling - 07 Aug, 2009 - Comments: 0

Low-Power Design sat down with Walter Ng, senior director of platform alliances at Chartered Semiconductor; Brani Buric, executive vice president of sales and marketing at Virage Logic; John Sanguinetti, CTO at Forte Design Systems and Andrea Kroll vice president of marketing and business development at JEDA Technologies. What follows are excerpts of that discussion. By Ed Sperling LPD: H... » read more

Newer posts →