October 2009 - Page 2 of 2 - Semiconductor Engineering

Considerations For Choosing The Right Low-Power Tools

By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Cheryl Ajluni Regardless of what you are designing these days, one fact holds true: Your design is only as good as the design tools you use. Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow. This is especially true when it comes to low-power design, as i... » read more

End User Report: Reliability

By Ed Sperling - 15 Oct, 2009 - Comments: 0

John Kern, vice president of product operations inside Cisco Systems’ customer value chain management group, sat down with Low-Power Engineering to talk about the company’s internal focus on reliability and what factors are causing the most concern. What follows are excerpts of that conversation. By Ed Sperling LPE: How does Cisco gauge reliability? John Kern: The bulk of our re... » read more

Battery Progress Inches Forward

By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Ed Sperling Chip companies that have been betting the future on better battery technology and holding off on the often painful process of reducing voltage should probably start rethinking their plans. Battery technology is not expected to improve by more than 3% per year, and even that may slow. Compared with the chip side, there are no breakthrough materials such as halfnium or techno... » read more

Defining Reliability In Low-Power Designs

By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Ann Steffora Mutschler Having a clear understanding of what reliability means for a particular low-power application can make a significant difference when it comes to communicating with engineering team members and customers. Is reliability simply a question of how long a device can run without errors? And what happens to reliability when power modeling, verification and other design tec... » read more

Experts At The Table: What’s Next?

By Ed Sperling - 15 Oct, 2009 - Comments: 0

Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation. By Ed Sperling LPD: Where... » read more

Things To Watch Out For

By Bhanu Kapoor - 15 Oct, 2009 - Comments: 0

By Bhanu Kapoor A decoupling capacitor (DeCap) is used in power-managed designs to decouple a power domain from the effects of power switching in a related domain. A switching sub-circuit (a power domain or a voltage island) can mess up the power supply line upon which other sub-circuits or domains depend upon. When a load switches into a circuit, the circuit tries to increase its curre... » read more

Multicore Meets Multichannel Memory

By Ed Sperling - 08 Oct, 2009 - Comments: 0

Rambus Fellow Craig Hampel talks with System-Level Design about the next bottlenecks in high-performance computing and how to solve them. [youtube vid=jbNg1xdZUoU] » read more

Verify, Verify, Verify

By Ed Sperling - 02 Oct, 2009 - Comments: 0

Verification has claimed the biggest chunk of design time and cost for many generations of chips, but it has now been elevated from design headache to the poster child of what’s ailing semiconductor design. The question being asked in many quarters, and also in many different ways, isn’t whether the verification approach and tools are right. It’s whether the fundamentals of design an... » read more