November 2009 - Semiconductor Engineering

Compression Effect
By Ed Sperling - 19 Nov, 2009 - Comments: 0

For all the talk of restricted design and increasing complexity, it seems that what’s really happening is that restrictions are being lifted off one group and placed on another. This happens from time to time in system-level design, usually at an inflection point in the overall system development process or at the start of a new process node. For the past couple decades, much of the crea... » read more

It’s All About Attitude
By Jack Harding - 19 Nov, 2009 - Comments: 0

By Jack Harding When I started my career at IBM, one of the favorite sales lines we used was, “No one ever lost their job because they chose IBM.” In the burgeoning business computer market, that was true. Why? It wasn’t the size of the company. Actually, we were forbidden to link customer success with IBM’s “bigness,” which was an artifact of the Consent Decree with the U.S. Dep... » read more

Verification Of Multi-Clock Designs: The Bigger Picture
By Various Writers - 19 Nov, 2009 - Comments: 0

Yesterday’s SoCs are today’s blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this is further complicated by multiple modes of operation and the associated range of clocking scenarios. This leads to ever increasing numbers of clock interfaces, where data is transferred betw... » read more

More Choices But Less Design Freedom
By Ed Sperling - 19 Nov, 2009 - Comments: 0

By Ed Sperling “What if” is an indelible part of the lexicon of every SoC architect and design engineer from the front end of the design flow all the way to manufacturing, but while the terminology will persist for years to come the answers and the value of those answers are starting to change. Complexity, cost and the need for better integration have simultaneously increased the numb... » read more

Methodology Shifts Ahead
By Pallab Chatterjee - 19 Nov, 2009 - Comments: 0

By Pallab Chatterjee The high cost of SoC development at advanced process nodes is forcing a significant shift in many of the methodologies used in design. Hierarchical design methods are giving way to IP integration and hierarchical analysis at the architectural and functional design levels. Previously, large blocks were implemented at the top level of the chip and the analysis was pushe... » read more

An ESL Measurement Epiphany
By Jon McDonald - 19 Nov, 2009 - Comments: 0

By Jon McDonald Sometimes something becomes so simple and clear it’s shocking. I recently experienced such an epiphany. It started with a typical discussion on hardware software relationships and tradeoffs. How do you know what should be done in which? Realistically there is no automatic method to determine the proper partition. The best we can do is to propose a potential solution, the... » read more

Return Of The Femtocell
By Cheryl Ajluni - 19 Nov, 2009 - Comments: 0

By Cheryl Ajluni Nothing has been left unscathed in the current global economic downturn, and that includes femtocell deployments. It was just last year that femtocells were being proclaimed a 2009 “killer app,” along with LTE and WiMAX. But what was once viewed as the next great thing has instead faced a tough road with more than a few large-scale deployments by major mobile operators be... » read more

Services To Render
By Ed Sperling - 17 Nov, 2009 - Comments: 0

Tools companies, value-chain producers and IP providers have fared pretty badly in the past when it comes to services. They’ve been paid for their products, but even software was considered a giveaway. And services were an extra that no one even considered charging or paying for, except in body-shop types of arrangements for hitting tapeout deadlines and last-minute debugging. That’s cha... » read more

Why Intel Is Settling With AMD
By Ed Sperling - 13 Nov, 2009 - Comments: 0

There’s more to the Intel-AMD settlement than meets the eye. While Intel will be paying out $1.2 billion to AMD as part of the settlement—and that’s a large chunk of money in anyone’s book—it’s a relatively small price to pay when it’s amortized over 10 years and can open the door to even bigger markets for Intel. And that’s just what this is, a down payment on the future. ... » read more

A Noticeably Cooler Continental Climate
By Ed Sperling - 12 Nov, 2009 - Comments: 0

Nicolas Leterrier, chief representative of the Minalogic coordination unit, whose job is to oversee the “innovation cluster” in Grenoble, France, sat down with Low-Power Engineering to discuss the changes under way in Europe, what's driving it and where researchers in Grenoble see the future challenges. What follows are excerpts of that interview. By Ed Sperling LPE: Is the impetus fo... » read more

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