December 2009 - Page 2 of 2 - Semiconductor Engineering

Reducing Power In Plasma Display Panels

By Various Writers - 10 Dec, 2009 - Comments: 0

By the EEFocus staff In early 2009 there was a lot of coverage in the media at home and abroad about plasma display panel (PDP) TV sets being banned in the EU. Paul Gray, Director of European TV Research, denied the claim but did mention that they were planning to set minimum energy efficiency standards for flat-panel TVs and set maximum energy consumption limits according to screen sizes. He ... » read more

Greener Data Centers

By Ed Sperling - 10 Dec, 2009 - Comments: 0

By Ed Sperling For decades the race inside the data center was all about performance. If you upgraded from an IBM Series/370 mainframe to a Series/380 your applications ran faster. And if you upgraded your PC server from a Pentium II to a Pentium 4 you got significantly better performance. The race now is to reduce the number of servers altogether, to lower the cooling costs per server ra... » read more

Differentiating Embedded Processors

By Ed Sperling - 10 Dec, 2009 - Comments: 0

By Ann Steffora Mutschler The embedded processor world addresses a vast range of applications – from the datacenter to the biomedical device – all of which have critical power needs that vary with the use. Power concerns continue to dominate the embedded system whether it is avoid a noisy fan in a TV set-top box, allow video on a mobile phone or minimize pricey cooling costs in the datac... » read more

Experts At The Table: Rising Complexity Meets Verification

By Ed Sperling - 10 Dec, 2009 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are ... » read more

Choosing A Power Delivery Network For SoCs

By Bhanu Kapoor - 10 Dec, 2009 - Comments: 0

By Bhanu Kapoor The design and selection of an SoC power delivery network (PDN) presents unique challenges, and its design is critical to achieving power consumption goals of the design. This is true when your PDN is external and based on off-the-shelf components as well as when it is being designed on-chip as part of the SoC. This article explores the external situation. Power archit... » read more

5 Reasons For Change

By Ed Sperling - 04 Dec, 2009 - Comments: 0

One of the most intriguing trends to watch these days is in the area of diversification and differentiation. As we emerge from the worst downturn in the history of semiconductor design—in fact, the only time EDA has ever shown negative numbers other than accounting changes—companies are looking for new avenues of revenue growth that are significantly different than where they drew their r... » read more

Experts At The Table: Rising Complexity Meets Verification

By Ed Sperling - 04 Dec, 2009 - Comments: 0

Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are excerpts of that ... » read more

With ESL, You Are Your Ecosystem

By Ed Sperling - 01 Dec, 2009 - Comments: 0

Where are the weak links in the ESL ecosystem? That question isn’t idle speculation. With complexity in many SoC designs reaching well beyond the level of human comprehension—even beyond the capabilities of the most brilliant engineers or architects—chip developers on all levels need to know what can go wrong from both a technology and a business standpoint. No company can dev... » read more

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