August 2010 - Page 2 of 3 - Semiconductor Engineering

Building A Better Team
By Ed Sperling - 25 Aug, 2010 - Comments: 0

One-On-One with IDT CEO Ted Tewskbury: How IDT is bridging the analog and digital engineering worlds with a mixed-signal team approach.   [youtube vid=TRfJ5a3WJrw] » read more

PathFinder: A Dynamic And Static Analysis Solution For IP And Full-Chip IC ESD Integrity
By Various Writers - 13 Aug, 2010 - Comments: 0

ESD or electro-static discharge induced field failures for integrated circuits (IC) has always been an challenge. Literature survey indicates that as high as 35% of total chip field failures are ESD related. Several trends in the IC industry are exacerbating the impact of ESD induced failures: (a) move towards advanced processing technologies with shrinking geometries, (b) push for higher le... » read more

Power Conference
By Barry Pangrle - 12 Aug, 2010 - Comments: 0

By Barry Pangrle Big 10, ACC, SEC, Big 12, Pac 10? Well, if you’re thinking of universities that’s a start in the right direction (and there will be a quiz at the end of this blog). If you reside outside of the U.S., I apologize for the local reference. When organizing any technical conference, there’s always a challenge in striking a balance between presenting research that may have... » read more

Power And Signal Line Electromigration
By Various Writers - 12 Aug, 2010 - Comments: 0

Power and Signal Line Electromigration Design and Reliability Validation Challenges for the 28nm-era Reliability verification is an important aspect in the design and development of an integrated circuit to guarantee its continued functioning over years of production use. One critical area of reliability verification is electromigration (EM) check analysis to ensure that the wires and vias u... » read more

Structural Verification Finds Mixed-Signal LP Errors
By Luke Lang - 12 Aug, 2010 - Comments: 0

By Luke Lang In the last blog, I gave some reasons why there is no low power (LP) analog/mixed-signal solution. However, this does not mean there is no effort in this area. Toward the end of 2009 and early 2010, I worked with a customer to establish a LP analog/mixed-signal structural verification flow. This flow was proven to be extremely helpful. It caught several LP bugs that were not found... » read more

Defining Power Intent
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler Designing power-sensitive SoCs has never been more challenging given the tremendous demand for power efficiency in applications ranging from smart phones to servers inside data centers. That makes describing the power control architecture of a chip through power intent essential. Specifically, explained Will Ruby, senior director of product engineering and applicat... » read more

Can IP Be Standardized In Low-Power Designs?
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler SoC designers are beginning to embrace low power formats UPF (IEEE P1801) and the Common Power Format (CPF) to express power intent, but are these efforts enough to create standardized IP in low power designs? Mike Brogley, IP and solutions product marketing manager at Actel, believes it is possible. “Yes, IP can be standardized, but the main driver in low-pow... » read more

New Low-Power Memory Interface Ahead
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Pallab Chatterjee The trend in consumer electronic devices is toward a multimedia-centric data flow, forcing changes in the memory interface needed to handle it. The increased compute resources needed for video signal processing, along with high-definition audio, used to be the exclusive domain of mainstream desktop computers and servers due to their access to memory and high data throug... » read more

Rethinking Models
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ed Sperling The move to future process nodes will require more than just new materials, better layouts and higher levels of abstraction. It also will require a fundamental re-thinking of how high-level architectural models are created and what’s included in them. While the Transaction-Level Modeling (TLM) 2.0 standard has provided significant improvements for everything from layout to ... » read more

One On One With South Korea’s CTO
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ed Sperling Chang-Gyu Hwang, national chief technology officer for South Korea, sat down with Low-Power Engineering to talk about the future trends in technology, global business and power. Prior to his current role, which was created by the Korean government in April, he ran the semiconductor business at Samsung, where he spent the last 20 years in top management positions. He also is the... » read more

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