November 2010 - Page 2 of 2 - Semiconductor Engineering


ARM’s Race


Prior to the Synopsys acquisition of Virage Logic, Synopsys seemed to have an almost exclusive relationship with ARM. Since then, Cadence and Mentor Graphics have both been cutting deals with ARM for support of its IP cores. What’s changed? With regard to the Virage Logic acquisition, very little. Synopsys did acquire the ARC processor through that deal, but ARC had been much more focused ... » read more

Power To Fly


By Barry Pangrle As technologies mature, they often follow similar profiles. Back on Oct. 14th I heard Lesley Curwen of the BBC interviewing Charles Champion, executive vice president of engineering at Airbus. Champion said that over the last 40 years the airline industry has reduced emissions and fuel burn by 70%. He pointed out that the industry initially focused on speed and the tendency no... » read more

The Trouble With Low-Power Verification


By Ed Sperling If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume? Answer: No one knows for sure. The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design. “Power... » read more

How Software Utilizes Cores


By Ann Steffora Mutschler When writing software, how does the design engineer determine how much power it will draw on a particular targeted platform? While the question seems straightforward, the answer is not. The industry is just starting to develop the ability to get some data in that space, according to Cary Chin, director of technical marketing for Synopsys’ low-power solutions gr... » read more

Low-Power Standards Watch: Ethernet


By Colleen Taylor With a job that can legitimately count "the inherent constraints of quantum physics" as a major cause of workplace stress, engineers in the semiconductor industry have never exactly had it easy. But as policymakers focused on curbing emissions impose increasingly strict regulations on the power consumption of consumer electronic devices, a host of new challenges have emerged ... » read more

Power-Delivery Network Challenges Grow


By Ann Steffora Mutschler Physics is forcing convergence in the SoC power delivery network, whose job is to ensure that every device on a chip has a robust and stable voltage so it can meet its expected functionality and timing. In the past, chip design, package design and board design were separate disciplines, guard-banded to ensure that all the parts worked well together. Today, given t... » read more

Making Software More Efficient


By Ed Sperling Software is being targeted by most of the major chip vendors and EDA companies as the next big opportunity for saving power, but exactly which software should be modified and by whom isn’t always clear. To some extent those answers depend upon which part of the software stack vendors or engineers believe can be adjusted most easily, and so far there is no widespread agreeme... » read more

Deep Dive: Energy Efficient Ethernet


By Pallab Chatterjee In late September, the IEEE ratified the 802.3az Energy Efficient Ethernet (EEE) specification. The standard, and associated test certification specification, was supported by co-development of over 20 commercial products from multiple vendors, of which 13 were release to market simultaneous with the ratification. Wael Diab, from the office of the CTO at Broadcom, and ... » read more

Making Power Delivery Networks Better


Careful design of power delivery networks can make the difference in whether a chip manages power effectively or fails completely. This impact of cost and other factors in the design process has not gone unnoticed. Aveek Sarkar, vice president of customer support and product engineering at Apache Design Solutions, pointed to the iPhone as an example, where 50% or more of the bill of material... » read more

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