December 2010 - Page 2 of 3 - Semiconductor Engineering

Reaching The Breaking Point
By Ron Craig - 16 Dec, 2010 - Comments: 0

By Ron Craig Atrenta recently conducted a user survey on timing constraints, in an effort to find out more about how they are being managed and where the issues are. I expected a diverse range of feedback on different use models, roadblocks etc., but it was very interesting to see some trends pop up: 94% of respondents said that timing constraints were a problem. About 30% of respondents... » read more

Why Is My Simulation So Slow?
By Jon McDonald - 16 Dec, 2010 - Comments: 0

By Jon McDonald I am amazed how often simulation performance comes up when discussing SystemC and transaction-level modeling. Some of this I can understand. If you are new to transaction-level modeling the implications can take a while to get a handle on. Fundamentally it is difficult to justify the investment in TLM if the models are not significantly simpler to write and significantly fas... » read more

Beyond 22nm
By Ed Sperling - 15 Dec, 2010 - Comments: 0

Gary Patton, VP at IBM's semiconductor R&D Center, talks with System-Level Design about the challenges of developing chips all the way down to 15nm. [youtube vid=2wTj3EvRIRw]   » read more

The Ever-Growing System Challenge
By Jon McDonald - 10 Dec, 2010 - Comments: 0

It used to be easy to define a system. It was an ASIC, an ASSP or even an SoC. Increasingly, however, that definition isn’t nearly broad enough. With power issues now spreading across an entire device and software being used to manage everything from embedded applications to board-level functionality, the system is now much bigger than a single chip or even a system in package. It now enc... » read more

Experts At The Table: IP Integration Hurdles
By Ed Sperling - 10 Dec, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversati... » read more

The Rising Stake In Software Tools
By Ed Sperling - 03 Dec, 2010 - Comments: 0

By Ed Sperling The growing importance of software and off-the-shelf IP in semiconductor design is beginning to change the dynamics of the entire EDA tools business, setting off a string of acquisitions as the largest players realign themselves to take advantage of this shift. The most recent example: Mentor Graphics’ acquisition this week of CodeSourcery, a GNU-based Linux toolchain and s... » read more

Power On
By Barry Pangrle - 02 Dec, 2010 - Comments: 0

By Barry Pangrle Process development is more challenging at each successive technology node but the march forward, for the time being, continues unabated. Voltage scaling stopped around the 100nm node at roughly 1.0v as threshold voltages stopped shrinking in an attempt to keep leakage in check. It’s been the progression to the newer and smaller technology nodes that has really pushed power ... » read more

What’s Your Toggle Rate?
By Luke Lang - 02 Dec, 2010 - Comments: 0

By Luke Lang Now that power is a key specification, designers are looking into various design techniques to reduce power. One thing that designers realize very quickly is that there is a cost associated with these low-power techniques. Some of these costs are silicon area and design complexity. Very quickly, designers face the tradeoff of cost vs. power saving. In order to analyze this tradeof... » read more

Getting Real About Power Management Verification
By Bhanu Kapoor - 02 Dec, 2010 - Comments: 0

By Bhanu Kapoor SoCs that are used in consumer electronics utilize power management techniques that require control of voltage sources. We have discussed the need for power-aware simulation for verification purposes in the past. EDA tools have advanced to include power-aware simulation such as those found with simulators like VCS from Synopsys. In this article, we discuss the need for modeling... » read more

The Deafening Problem Of High-Speed I/O
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler The performance of digital systems today is limited by the interconnection bandwidth between chips, boards, and cabinets. This has driven I/O speeds up into the gigabytes. While this boosts performance, it also opens the door to a host of new problems within the chip, board and system. Add low-power requirements to the mix and it is a recipe for huge headaches. One... » read more

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