March 2012


Experts At The Table: Designing At 28nm And Beyond


By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), an... » read more

EUV glass still less than half full, but level is rising


EUV first drew the semiconductor industry’s attention in the late 1990s, as lithographers began to consider the “post-optical” future. At that time, the future was expected to arrive with the 100-nm technology node, by 2004. ArF lithography turned out to be far more extensible than anticipated, though, and is still going strong fifteen years later. Which is fortunate given that, as we now... » read more

Enterprise Power


The corporate data center is getting a lot of attention these days. ARM is fighting for a place inside server racks. Cadence has rolled out IP for faster storage standards. And Mentor Graphics has just introduced middleware for embedded Linux. Why? Because unlike the mobile space, where you need billions of units to make margins, in the corporate enterprise you only need millions. Those extr... » read more

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead


The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily bea... » read more

Lithography: How Slow Can We Go?


Moore’s Law has always been about economics:  if we follow the trend of Moore’s Law, we can reduce the cost per function for our integrated circuits, making chips more powerful for the same cost, or making chips of a given capability cheaper.  Historically, cost per function has decreased by about 29% per year, corresponding to a factor of 2 decrease in cost every two years.  There are s... » read more

Experts At The Table: IP


By Ed Sperling Low-Power Engineering sat down to talk about IP with John Goodenough, vice president of design technology and automation at ARM; Simon Butler, CEO of Methodics; Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys, and Neil Hand, product marketing group director at Cadence. What follows are excerpts of that discussion. LPE: The su... » read more

Experts At The Table: Designing At 28nm And Beyond


By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), an... » read more

Making Sense Of Virtualization


By Achim Nohl In the last month I’ve had the opportunity to get some hands-on experience with hardware virtualization and hypervisors. My knowledge so far on this has been mainly limited to what I could read about it and what other people are saying about it. However, the PowerPoint slides I’ve seen leave a lot of white fog between the bullet items. This didn’t make me feel very comfo... » read more

Managing Complexity With Advanced Packaging


By Ann Steffora Mutschler Engineering teams across the globe continue to pound the process geometry treadmill to stay on the curve of Dr. Moore to achieve better speed or lower power or smaller die—and it all adds up to increased complexity in the design and packaging. However, with advanced forms of die stacking such as package-on-package, silicon-in-package, 2.5D silicon interposer techno... » read more

Coherency Becomes A Stack Of Issues


By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

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