May 2012 - Page 2 of 6 - Semiconductor Engineering

The 28nm Foundry Crunch
By Ed Sperling - 29 May, 2012 - Comments: 0

By Mark LaPedus Faced with huge and unforeseen demand at the 28nm node, leading-edge foundries are scrambling to play catch-up and are boosting their fab capacities at a staggering pace. But analysts warn that 28nm foundry capacity will be tight throughout 2012, and perhaps into 2013, putting some chipmakers in a pinch. Many blame the 28nm foundry capacity shortfall on a combination of t... » read more

28nm Super Low Power CMOS
By Various Writers - 29 May, 2012 - Comments: 0

28nm Super Low Power (28nm-SLP) is the low-power CMOS offering delivered on bulk silicon substrate for mobile consumer and digital consumer applications. GlobalFoundries' 28nm-SLP process technology is designed for the next generation of smart mobile devices, enabling designs with faster GHz processing speeds, higher circuit density, lower standby power and longer battery life. The 28nm process... » read more

Planar Fully Depleted Silicon Technology To Design Competitive SoCs At 28nm And Beyond
By Various Writers - 29 May, 2012 - Comments: 0

This document considers the challenges to obtain competitive silicon technology for the upcoming generation of System-On-Chip ICs. It suggests planar fully depleted technology deserves serious interest. After outlining some implementation choices, a number of circuit-level benchmark results as well as some important design aspects are presented. It is found that this technology combines high pe... » read more

Finding And Eliminating Hot Spots
By Various Writers - 29 May, 2012 - Comments: 0

With the continuous development of today’s technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure during fabrication. In the current process, schematic designers go through extensi... » read more

Bigger Shifts Ahead
By Ed Sperling - 29 May, 2012 - Comments: 0

At 130nm the manufacturing portion of the semiconductor industry struggled with copper interconnects, 300mm wafers and immersion lithography. At 20nm and 14nm it will have to grapple with double, triple and possibly even quadruple patterning, new gate structures, the usual increases in process variation, far more expensive designs, complex challenges in attaining reasonable yields and in connec... » read more

FinFETs And 3D ICs
By Ed Sperling - 28 May, 2012 - Comments: 0

Semiconductor Manufacturing and Design talks with Soitec's Steve Longoria about the role of FD-SOI in advanced semiconductor design and 3D stacks. [youtube vid=P7Ld14s9NY4] » read more

The Brave New World Of Modeling TSVs
By Ed Sperling - 26 May, 2012 - Comments: 0

By Ann Steffora Mutschler With 2D ICs the prevailing notion has been that wire parasitics are relatively self-contained with the exception of very advanced designs running at hundreds of gigahertz. For the most part, the package designer and IC designer lived in their own separate worlds. With the advent of chip stacking using through silicon vias (TSVs), those worlds are being thrust together... » read more

Experts At The Table: The Future Of SystemC
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ed Sperling System-Level Design moderated a discussion about the future of SystemC with Thomas Alsop, corporate design solution expert at Intel; Ambar Sarkar, chief verification technologist at Paradigm Works; Mike Meredith, vice president of technical marketing at Forte Design systems; David Black, certified training instructor at Doulos. Here are some of the key outtakes of that discussio... » read more

Packaging Tradeoffs More Complex Than Ever
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

IaaS vs. SaaS
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler There has been a lot of confusion about what kind of cloud-based service the EDA industry offers. Here are two different business models. Infrastructure as a service (IaaS) In this most basic cloud service model, cloud providers offer computers – as physical or more often as virtual machines, raw (block) storage, firewalls , load balancers, and networks. IaaS pr... » read more

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