July 2012 - Page 2 of 5 - Semiconductor Engineering

Looking Into The Future
By Ed Sperling - 31 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design sat down with Juan Rey, senior director of engineering for Calibre at Mentor Graphics, about multipatterning, design rules and silicon photonics. [youtube vid=KoH5TwmFWDM] » read more

Investment Options
By Ed Sperling - 31 Jul, 2012 - Comments: 0

It's clear that something fundamental has changed in the semiconductor manufacturing industry. What's less clear is how this will play out over the long term. Intel's agreement to invest more than $4 billion in ASML to ensure the continued development of EUV and 450mm wafer technology is more than just a one-off deal. It's a very public recognition that the astronomical cost of design and ma... » read more

Experts At The Table: Pain Points
By Ed Sperling - 27 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: What comes next requires a lot of guesswork in the design, do... » read more

Experts At The Table: Coherency
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: What’s driving coherency and what sort of issues are you encou... » read more

Experts At The Table: Stacking The Deck
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler There is no doubt 3D stacking brings challenges not only from the design perspective, but also on the tool side. EDA vendors have been working for more than a few years to ready tools for stacked-die designs. How smooth the transition is, however, is a big question mark. Because the approach is new, not all the challenges are fully understood yet. And while most ED... » read more

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

SoC Platforms Gain Steam
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Platforms are attracting far more attention from makers of SoCs because they are pre-verified and can speed time to market, but the shift isn’t so simple. It will spark major changes in the way companies design and build chips, causing significant disruption across the entire SoC ecosystem. Platforms are nothing new in the processor and software world. Intel, IBM AMD, and N... » read more

Wreaking Havoc
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler With PCB circuits running at very fast speeds today, the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with specific physical layout requirements that are not obvious. There are unexpected challenges, important high-speed considerations and efficient ways to account for them in high-spe... » read more

Smarter Co-design With Models
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler IC, package and PCB co-design methodologies are starting to be adopted by semiconductor companies. However, the existing die abstract file used in these flows to exchange data between the IC designer and the downstream package design team may not contain enough detail to drive advanced planning and optimization with the package and PCB interfaces. Engineering teams... » read more

printf(“I Like”);
By Achim Nohl - 26 Jul, 2012 - Comments: 0

By Achim Nohl Debugging software by adding printf statements in the code is not considered the cleanest and most advanced debugging approach, but when you are searching for the root cause of a problem you often look to the debugging method you are most familiar with and can apply easily. The hurdle of setting up a complex debug or trace tool is counterproductive when dealing with schedule c... » read more

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