November 2012 - Page 2 of 5 - Semiconductor Engineering

Taming The Challenges Of 20nm Custom/Analog Design
By Various Writers - 29 Nov, 2012 - Comments: 0

Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The solution lies not just in improving individual tools, but in a new design methodology that allows rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers. To view this white paper, click here. » read more

Questa Covercheck: An Automated Code Coverage Closure Solution
By Various Writers - 29 Nov, 2012 - Comments: 0

This white paper explores the debugging aspect of code coverage closure, and how Questa CoverCheck’s unique ability of formal technology can automatically generate simulation exclusion files to improve code coverage results while reducing the amount of time wasted trying to hit unreachable states. To download this white paper, click here. » read more

The Agony Of Choice
By Frank Schirrmeister - 28 Nov, 2012 - Comments: 0

By Frank Schirrmeister In my last post on “The Complexity of System Development and Verification” I outlined five main use models for verification at four levels of scope, enabled by seven execution engines. So how exactly do users choose between the different execution engines to run hardware and software together before the actual chip is available? It is far from trivial. The seven engi... » read more

The Growing Verification Challenge
By Ed Sperling - 28 Nov, 2012 - Comments: 0

System-Level Design talks with Charles Janac of Arteris, Frank Schirrmeister of Cadence, Venkat Iyer of Uniquify and Adnan Hamid of Breker Verification Systems about the growing difficulty of verifying complex SoCs and what lies ahead. [youtube vid=zUB4_t9teE8] » read more

Considerations for Porting a Bulk CMOS Design to FD-SOI
By Various Writers - 16 Nov, 2012 - Comments: 0

Technologists describe a straight port of an existing bulk CMOS design to FD-SOI at the same node, obtaining the value of fully depleted SOI for a modest redesign effort. Considerations Bulk to FD - Release » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 16 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What effe... » read more

New Apps For 3D Chips
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing and; Design sat down to discuss the 3D device challenges and applications with Peter Ramm, head of the department for device and 3D integration at Fraunhofer EMFT Munich, one of Europe’s largest research organizations. SMD: Fraunhofer was a pioneer in 3D chip R&D, right? Ramm: We are the oldest microelectronics institute in Germany. We st... » read more

How To Make A Brain-On-A-Chip
By Mark LaPedus - 15 Nov, 2012 - Comments: 0

By Mark LaPedus In October, Draper Laboratory and the University of South Florida (USF) disclosed an ambitious plan to develop a brain-on-a-chip. The idea is to devise a “micro-environment’’ that mimics the human brain. Researchers hope to study neurodegenerative conditions such as Alzheimer’s disease, strokes and concussions. The eventual goal is to study the effects of drugs and v... » read more

Node Skipping Reaches New Heights
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence. The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skip... » read more

Facing Up To RC Delay
By Ed Sperling - 15 Nov, 2012 - Comments: 0

y Ed Sperling Resistance and capacitance delays have always been someone else’s problem to solve at some fuzzy process node in the future, and for the most part manufacturers and equipment makers have done a wizard-like job of making this problem go away. They can’t make it disappear anymore, though, and beginning at 14nm and beyond RC delay is becoming more than just an annoyance. The ... » read more

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