February 2013 - Page 2 of 6 - Semiconductor Engineering

Power Management: Throwing Down The Gauntlet
By Frank Ferro - 28 Feb, 2013 - Comments: 0

By Frank Ferro The recent burst of articles challenging smart phone battery life has me asking the question, “Are we ready to turn the corner on power consumption?” About two years ago I was bemoaning the fact that we are willing to live with a smart phone that gets only one day of battery life (Powering Forward or Moon Walking). As of today, nothing has changed. We still need to charge th... » read more

Modeling Errors
By Ed Sperling - 28 Feb, 2013 - Comments: 0

Raising the abstraction level in increasingly large and complex design requires proxies. In IC world, we think of them in terms of higher abstractions, but the basic premise is that you can’t focus on ever detail without losing sight of the bigger picture, so we build models that can represent those details. Done well, these models are incredibly useful. They save time, make it easier to ... » read more

Designing with FinFETs: The Opportunities and the Challenges
By Various Writers - 28 Feb, 2013 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

Blocking Vs. Non-Blocking
By Various Writers - 28 Feb, 2013 - Comments: 0

By analyzing two flow control protocols – Single Threaded Tag (STT) and Multi-Threaded Non-Blocking – we describe a typical SoC employing the two protocols and evaluate their relative advantages and disadvantages. We evaluate the two protocols by experimentation with a representative digital TV (DTV) design and its derivatives, and then show you how one system is able to achieve better perf... » read more

Clock And Reset Ubiquity: A CDC Verification Perspective
By Various Writers - 28 Feb, 2013 - Comments: 0

Today’s SoC integrates a collection of peripherals, memory, graphics, networking and I/O components that originate from a multitude of sources. It could comprise designs from within the company, from other companies or from third-party IP vendors. These independently developed components come together to enable a rich feature set for the SoC. However, accompanying this abundance of features i... » read more

Chip Economics
By Various Writers - 28 Feb, 2013 - Comments: 0

The concise research paper, "NoC Interconnect Improves SoC Economics: Initial Investment is Low Compared to SoC Performance and Cost Benefits," by Objective Analysis Semiconductor Market Research, provides quantitative data from user experiences comparing the costs and benefits of implementing network on chip SoC interconnects versus traditional bus and crossbar interconnects. You will learn... » read more

Ready For 3D-IC
By Various Writers - 28 Feb, 2013 - Comments: 0

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers. To download this white paper, click here. » read more

Development Tools Enabling The Internet of Things
By Frank Schirrmeister - 27 Feb, 2013 - Comments: 0

I'm at the Embedded World conference in Nuremberg this week. Yes, between Mobile World Congress in Barcelona and DVCon in San Jose, Calif., I chose Embedded World. Unfettered by unseasonally late snow and bad weather, it turns out this was the right decision. I have not attended this show for a couple of years and am pleased to find that the show has developed quite a bit. There are more than 8... » read more

Verifying Complex Chips
By Ed Sperling - 27 Feb, 2013 - Comments: 0

System-Level Design talks about what's changing in SoC verification with Janick Bergeron, verification fellow at Synopsys; Harry Foster, chief verification scientist at Mentor Graphics; Pranav Ashar, chief technology officer at Real Intent; Raik Brinkmann, president and CEO of OneSpin Solutions, and Tom Anderson, vice president of marketing at Breker Verification Systems. [youtube vid=DzDYyf... » read more

SPIE Advanced Lithography 2013 – day 1
By Chris Mack - 26 Feb, 2013 - Comments: 0

Day 1 of the SPIE Advanced Lithography Symposium began, as always, with the plenary session.  Bill Arnold, former lithography manager at AMD and now CTO at ASML, gave a “state of the union” address – he is this year’s SPIE president.  (Congratulations, Bill – I voted for you!)  The 10th Zernike Award for achievements in microlithography went to Dave Markle, a well-deserved honor (f... » read more

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