March 2013 - Page 2 of 6 - Semiconductor Engineering

Observation Post
By Pranav Ashar - 28 Mar, 2013 - Comments: 0

By Pranav Ashar After attending the 2013 Design and Verification Conference (DVCon) in San Jose, Calif., I have compiled notes as both an observer and a panel participant. Here are my observations: Wally Rhines, CEO of Mentor Graphics, gave the keynote presentation: Accelerating EDA Innovation Through SoC Design Methodology Convergence. Logically and effectively he made the case that SoC in... » read more

Staying Neutral
By Kurt Shuler - 28 Mar, 2013 - Comments: 0

By Kurt Shuler It’s official: The great IP land grab has begun. The process actually has been taking place gradually, but has accelerated with Imagination Technologies’ acquisition of MIPS last year and, most recently, Cadence’s acquisition of Tensilica. For makers of semiconductors, four competing IP behemoths are emerging after years of fragmentation within the semiconductor IP indu... » read more

The Business Of Things
By Frank Ferro - 28 Mar, 2013 - Comments: 0

By Frank Ferro The Internet of things (IOT) will create $14 trillion dollars in business opportunities according to Cisco. Unless you are a government accumulating debt, most of us think that’s a big number—and a big opportunity. The much quoted “50 billion connected devices to the Internet by 2020” forecast is the impetus driving companies in all parts of the ecosystem including infra... » read more

The Best Abstraction
By Jon McDonald - 28 Mar, 2013 - Comments: 0

By Jon McDonald The other day I was asked what would be the best level of abstraction to model at for system-level design. This is a question I get, in one form or another, far too often. It reminds me of an old quote attributed to Lincoln, slightly updated and applied to this subject: “One model can answer some of the questions all of the time, and all of the questions some of the time, but... » read more

Market Realities
By Ed Sperling - 28 Mar, 2013 - Comments: 0

The speculation about EDA’s future—will it consolidate, will it be incorporated into large IDMs or foundries—has surfaced again. The reason this time is that EDA is in a retrenchment period as the semiconductor industry grapples with increasing complexity, multiple options ranging from multi-patterning to stacked die to more third-party IP, and the rising cost of complex SoCs at the mo... » read more

How To Reduce The Need For Guardbanding A Flash ADC Design
By Various Writers - 28 Mar, 2013 - Comments: 0

For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is growing with the increasing interactions among devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, and accurate parasitic extraction is critical for first silicon success. New 3D parasitic extraction technology applied to a flash ADC circ... » read more

Solutions For Mixed-Signal SoC Verification
By Various Writers - 28 Mar, 2013 - Comments: 0

Performing full-chip verification of large mixed-signal systems on chip (SoCs) is an increasingly daunting task. As complexity grows and process nodes shrink, it’s no longer adequate to bolt together analog or digital “black boxes” that are presumed to be pre-verified. Complex analog/ digital interactions can create functional errors, which delay tapeouts and lead to costly silicon re-spi... » read more

Solutions For Mixed-Signal IP, IC, And SoC Implementation
By Various Writers - 28 Mar, 2013 - Comments: 0

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Realizing modern mixed-signal designs requires new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implem... » read more

Physical Verification Of FinFETs And Fully Depleted SOI
By Various Writers - 28 Mar, 2013 - Comments: 0

It has become very difficult to effectively shrink traditional bulk planar transistors below 20nm due to physical effects that become dominant in very short conduction channels. The major impediment is an unacceptable rise in power consumption due to significant leakage currents. New transistor architectures are being adopted that offer a solution for these short-channel effects and allow trans... » read more

Trying To Catch Up With Software Developers
By Frank Schirrmeister - 27 Mar, 2013 - Comments: 0

By Frank Schirrmeister The electronic design automation (EDA) industry has now been trying for at least a decade and a half to catch up with software developers, for two main reasons. First, there are so many of them that it would be great to expand EDA into that domain. Second, semiconductor companies, i.e. the core customers to which the EDA industry sells, have had to add more and more soft... » read more

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