May 2013 - Page 2 of 6 - Semiconductor Engineering

Just Add IP
By Kurt Shuler - 30 May, 2013 - Comments: 0

When discussing SoC design with my semiconductor design and software development peers, the conversation eventually gets around to the problem of, “There’s just too much IP!” The feelings I hear border on exasperation at the problem of integrating IP on today’s large SoCs. Engineers who were once paid to write lines of Verilog or C code from scratch are now spending much of their time t... » read more

Multicore: Is More Better?
By Frank Ferro - 30 May, 2013 - Comments: 0

By Frank Ferro Two cores are better than one, right? It reminds me of those AT&T commercials where they ask the kids, “Who thinks two is better than one?” And of course the kids all yell, two! In another version of the commercial they ask; “What’s better, doing two things at once or just one?” And again they all yell, two! Well, this is a good summary or of last week’s Multicor... » read more

Does SoC Signoff Mean More Than RTL?
By Graham Bell - 30 May, 2013 - Comments: 0

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to carry errors forward from one stage to the next, where their impact grows while their causes become more obscured. This requirement is driving the shift in design exploration and handoff to the reg... » read more

Development of Complex Multicore Systems: Tracing Challenges and Concept
By Various Writers - 30 May, 2013 - Comments: 0

This white paper is the first paper of a two-part Mentor Embedded multicore white paper series. In this paper, the challenges software developers face when developing, debugging, and validating software applications for a complex multicore system will be discussed. The paper also highlights some of the questions around hardware resource usage, tracing aids, tracing domains, and concepts for col... » read more

FinFET Technology
By Various Writers - 30 May, 2013 - Comments: 0

This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to... » read more

Executive Briefing: Stacking The Odds
By Ed Sperling - 29 May, 2013 - Comments: 0

Open-Silicon CEO Naveed Sherwani talks with System-Level Design about progress on 2.5D and 3D stacked die, why this approach is inevitable, when it will begin and what markets will use it first. [youtube vid=mzwpgDKuIok] » read more

IP Play
By Ed Sperling - 29 May, 2013 - Comments: 0

Cadence Senior Vice President Martin Lund talks about the future of IP, why his company has been on an IP acquisition binge, and the new focus on mass-customization. [youtube vid=FdmBIlXpGVk] » read more

Design strategy for low e windows with effective insulation
By Michael Watts - 29 May, 2013 - Comments: 0

Whether you want to save your wallet, or save your planet; effective insulation of structures is essential. It turns out that windows are much more interesting and challenging design problem than I appreciated. This is a 2 part story, if you hate serials, the whole story is at www.impattern.com. As a warm blooded species, our body temperature (37C/98F) determines the temperature that we feel... » read more

DFM Success At SMIC
By Mentor, a Siemens Business - 28 May, 2013 - Comments: 0

Jeff Wilson As any integrated circuit (IC) designer knows, design rules are the “first line of defense” foundries provide in the effort to ensure all IC designs are ultimately manufacturable. Coming in a close second, design for manufacturing (DFM) rules enable designers to maximize design capabilities and performance while minimizing or optimizing the use of chip space. At today’s ad... » read more

Big Iron Conundrums
By Ed Sperling - 24 May, 2013 - Comments: 0

Enormous attention is being focused on energy efficiency in mobile devices because time between charges trumps a slight boost in performance. Inside of data centers those benefits are far less clear. While energy costs remain a huge factor—they are a visible part of the bottom line costs for a CIO—how to reduce those costs is anything but a simple equation. Just adding more energy-saving... » read more

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