June 2013 - Page 2 of 6 - Semiconductor Engineering

Best-In-Class Tools Lead To Best-In-Class Design?
By Graham Bell - 27 Jun, 2013 - Comments: 0

Today’s systems on chip (SoC) are deeply complex in new ways. A dozen or so years ago, a state-of-the-art processor such as the Intel Pentium 4 used 42 million transistors, was built on a 180nm process and relied upon discrete chips to handle its system interfaces. Jump forward, and the Intel Xeon Phi processor that Intel introduced in 2012 uses 5 billion transistors and is built on a 22nm pr... » read more

DAC Is Dead? Long Live DAC!
By Kurt Shuler - 27 Jun, 2013 - Comments: 0

By Kurt Shuler I have long decried the declining attendance at the ACM/EDAC/IEEE Design Automation Conference (DAC), especially in regard to this trend’s adverse effect on continuing professional education (CPE) opportunities for our industry’s engineers. (See my May 2011 article, “The Trouble With Tradeshows, for more.) In fact, for those of you who know me personally, I have sometimes ... » read more

Life After Smartphones
By Frank Ferro - 27 Jun, 2013 - Comments: 0

By Frank Ferro Don’t let the title confuse you. Smartphones are not going away anytime soon. In fact this year’s smartphone shipments have exceeded feature phones for the first time, with a total of 216 million units in Q1, according to IDC, and the overall mobile phone market is expected to grow 4.3% in 2013. This volume represents an increase in smartphone sales of 42% from Q1 2012. ... » read more

Faster Assembly Required
By Ed Sperling - 27 Jun, 2013 - Comments: 0

Speeding up production has been a mantra dating back throughout recorded history, and presumably well before that. That’s what technology was created for—roads, bridges aqueducts, computers, the Internet, and everything that connects the real to the virtual world. A speech by Nvidia chief scientist Bill Dally at DAC that complex SoCs should only take a couple weeks to design by two guys ... » read more

Garbage Or Treasure?
By Jon McDonald - 27 Jun, 2013 - Comments: 0

By Jon McDonald “Garbage in, garbage out” is a very appropriate axiom to keep in mind as you consider what kind of system-level modeling to invest in. Unfortunately this can be complicated by considering another piece of wisdom that often applies as well: “One mans trash is another’s treasure.” What might be an inappropriate abstraction for one type of analysis may be very accepta... » read more

From Design to Test: Developing High-Reliability MTP NVM
By Various Writers - 27 Jun, 2013 - Comments: 0

In developing high-quality and reliable MTP NVM, NVM IP providers must account for design and architectural considerations as well as comprehensive silicon testing. To help system-on-chip (SoC) designers select the highest reliability NVM IP, this white paper will review the key considerations involved in the entire process from design to test, including: key reliability specifications; designi... » read more

The Rise Of The Subsystem And New IP Providers
By Frank Schirrmeister - 26 Jun, 2013 - Comments: 0

By Frank Schirrmeister From the perspective of system development in EDA, the customer landscape and its changes have always had a fascinating influence on our tools. NVIDIA’s recent announcement in a corporate blog post that they will be licensing the Kepler GPU architecture caused me to check again on the customer landscape for which we are enabling system development, for example, with ou... » read more

OLED Displacing LCD, But Not Affecting Industry Leaders
By Michael Watts - 25 Jun, 2013 - Comments: 0

By Michael P.C. Watts One of the most common themes in high tech is how companies fail to deal with game-changing new products. Think about Kodak and digital cameras, Sony and the flash memory music player, Microsoft and the tablet, GE and Osram and the Light Emitting Diode (LED). The overwhelming conclusion seems to be that you have to be committed to making your own most valuable product red... » read more

Experts At The Table: Performance Analysis
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

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