November 2013 - Page 2 of 10 - Semiconductor Engineering

The Week In Review: System-Level Design
By Ed Sperling - 22 Nov, 2013 - Comments: 0

Synopsys rolled out new non-volatile memory IP that cuts power by 90% and reduces area in half. The company said it accomplished this feat with a single-bit read capability, which can drop read operation down to 0.9 volts and peak current to less than 10 microamps during erase and programming. The target of the ultra-low power IP is RFID and near-field computing ICs. Mentor Graphics posted p... » read more

The Week In Review: Manufacturing & Design
By Mark LaPedus - 22 Nov, 2013 - Comments: 0

Intel is getting serious about the foundry business.  “Intel CEO Brian Krzanich is making some waves. This is not because Intel is becoming more market driven, but that Intel will open its foundry to ‘any’ company able to utilize the company's leading-edge technology. It’s very refreshing to see Intel make this move and could have important implications for the industry. Based on Intel... » read more

Is There Light At The End Of Moore’s Tunnel
By Brian Bailey - 22 Nov, 2013 - Comments: 2

Electrons are slow, clumsy and quite easily distracted. They’re slow because it now takes a signal longer to cross a chip than the period of the clock signal. They often don’t travel in straight lines as they collide with other atoms. And electromagnetic interference between adjacent signals can mess with the information they are transferring. On the other hand, light has none of these p... » read more

Sometime More Is More And Less…
By Neil Hand - 22 Nov, 2013 - Comments: 0

Anyone who has been reading this blog has already figured out that as an ex-system designer, I am a fan of intelligent IP subsystems, and in a couple of my previous posts I already talked about how they make design easier by distributing the overall complexity. The other day however, I found myself trying to describe to a non-semiconductor person why this move is good and what benefits it de... » read more

Even Standard IP Isn’t Always Standard
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

Improving Design Reliability By Avoiding Electrical Overstress
By Various Writers - 21 Nov, 2013 - Comments: 0

Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage ... » read more

Do Students Need More Formal Education?
By Brian Bailey - 21 Nov, 2013 - Comments: 0

A few weeks ago, some of the top researchers and practitioners in the area of formal methods converged on Portland, Oregon. The event was the annual Formal Methods in Computer-Aided Design (FMCAD) conference and Semiconductor Engineering attended the panel titled “Teaching Formal Methods: Needs, Challenges, Experiences, and Opportunities.” Panelists included: Jason Baumgartner, formal verif... » read more

Gartner Recommends Network-on-Chip (NoC) Technology For SoC Design
By Kurt Shuler - 21 Nov, 2013 - Comments: 0

In their latest Hype Cycle for Semiconductors and Electronics Technologies report, Gartner Research has taken the bold step of recommending that all enterprises involved in advanced SoC design should seriously evaluate network-on-chip (NoC) technology based interconnect fabric IP: “The technology has continued to receive a good amount of publicity along with continued adoption by leading S... » read more

HDMI 2.0 Design And Verification Challenges
By Various Writers - 21 Nov, 2013 - Comments: 0

HDMI designs face challenges with respect to run time and memory consumption due to the huge size of HDMI frames. Scrambling adds more complexity and designs face synchronization and timing challenges. Similar challenges are faced during the functional verification of systems-on- chip (SoCs) including HDMI interfaces. These challenges can be addressed using HDMI verification IP (VIP). To dow... » read more

Rethinking Old Sayings
By Jon McDonald - 21 Nov, 2013 - Comments: 0

One of my favorite quotes from Gary Smith is a few years old: “It’s the software, stupid!” That statement was made way back in 2006. While it was, and in some ways still is, very illustrative, I believe it also points to one extreme in the back and forth between focusing on hardware then software to differentiate our electronic systems. At the point in time Gary made the statement that... » read more

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