March 2014 - Page 2 of 9 - Semiconductor Engineering


Commoditizing Our Kids


My son is graduating from high school this year. He’ll be starting on an engineering degree in the fall. Thinking about the outlook he will face reminds me of questions and comments I have received from customers and colleagues at various points. In my mind these thoughts reduce to a simple question: Is engineering skill becoming a commodity? From Wikipedia: “The exact definition of th... » read more

How Much Will That Chip Cost?


From the most advanced process nodes to the trailing edge of design there is talk about the skyrocketing cost of developing increasingly complex SoCs. At 16/14nm it’s a combination of multi-patterning, multiple power domains and factoring in physical and proximity effects. At older nodes, it’s the shift to more sophisticated versions of the processes and new tools to work within those proce... » read more

EDA Shapes Its Future


In part one of this series, Semiconductor Engineering looked at growth within the EDA industry and the types of approaches being made to expand the scope of the markets that they serve. Scope expansion comes from the creation of new tools, the growth of companies in the IP space and the various ways in which opportunities can be found in new markets. Additional growth opportunities come from so... » read more

Distortion Effects Prevail In RF Design


It’s an exciting time for consumers of wireless devices, but it’s a challenging time for system designers who must design, analyze and verify that all of the components in those wireless devices interoperate. In wireless designs, distortion effects play an important role in the performance of RF circuits, including mixers, low-noise amplifiers (LNAs) and power amplifiers (PAs) and managi... » read more

The Great Shift To The Left


Writing this while I am at DATE in Dresden, Germany, I am also preparing for two panels on system-level trends later today and one on software-driven verification tomorrow. I am also visiting partners and customers to discuss our current and planned technologies. A while ago I had augmented “Leibson’s Law” stating that it takes 10 years for any disruptive technology to be adopted by desig... » read more

Biggest Verification Mistakes


[getkc id="81" kc_name="SoC"]s today have more processors and more embedded software than ever, including drivers and middleware just to get the hardware working. This, in turn, requires more and better [getkc id="10" kc_name="verification"]. Add to the challenge the fact that there is no one way to do verification and it is easy to comprehend how critical it is to for hardware and software tea... » read more

Formal Is Set To Overtake Simulation


There has been a significant psychology change in the area of formal verification over the past couple of years. It’s no longer considered a fringe technology, and it’s no longer considered difficult to use. In fact, it has become a necessary part of the verification process. Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we c... » read more

Better Software. Faster!


As virtual prototyping has seen a wide adoption over the last couple of years, it felt like the right time to work with industry leaders across multiple applications and publish a book that captures the best practices in virtual prototyping. As editor of the book: Better Software. Faster!, I had the privilege to work with some incredibly knowledgeable people who have been deploying virtual prot... » read more

The Week In Review: Design


Tools Synopsys rolled out a major new release of its place and route tool, the centerpiece of its physical design platform, offering up to 10X improvement in speed—a combination of 5X faster implementation and 2X larger capacity. Co-CEO Aart de Geus called it the most significant product in the company’s history. Synopsys also rolled out an AMS verification platform to accelerate regres... » read more

Getting A Handle On RTL X-Verification Challenges


The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed. In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering ... » read more

← Older posts Newer posts →