September 2014 - Page 2 of 11 - Semiconductor Engineering


Which Comes First?


Methodologies in IC design typically follow tools. The tools enable the methodologies, and chipmakers' businesses are built around both of them. That has been the rock-solid foundation for the design and production of chips since well before the impenetrable 1-micron wall. But that approach is falling apart at 28nm, and it will continue to crumble at 16/14nm and 10nm. It simply isn't fast en... » read more

How To Cut Verification Costs For IoT


Cost is one of the main factors limiting proliferation of the [getkc id="76" comment="Internet of Things"] (IoT), and when looking at the design and [getkc id="10" kc_name="Verification"] methodologies in place today, verification is a prime candidate for closer inspection. For today’s complex [getkc id="81" kc_name="SoCs"], the cost of verification has been rising faster than design and it h... » read more

Challenges Increase for IP At Advanced Nodes


At advanced process nodes such as 16/14/10nm, designing [getkc id="43" comment="IP"] is a much tougher nut to crack due to complexity and other considerations, not to mention then trying to migrate and/or re-use that IP. Still, engineering teams are looking for leverage wherever they can find it in their designs amid the technical challenges to overcome. Tomasz Wojcicki, vice president of c... » read more

IoT Demands Correct By Construction Assembly


The article Limiters To The Internet Of Things outlined several factors that are slowing the rate of deployment for the [getkc id="76" kc_name="IoT"]. Those limiters are cost, power delivery and storage, standards, security, and the limits of your imagination. This article picks up on a comment made by [getperson id="11244" comment="Chris Rowen"], fellow at [getentity id="22032" e_name="Cadence... » read more

Evaluation Platforms Key To Complex IP Integration


Just because a chip is complex to build doesn’t mean it has to take a long time. Runaway complexity in SoC and ASIC design is forcing chip companies to consider different methodologies and approaches that could actually simplify and speed up the whole process. The first step in this process was commercial IP, and its growing popularity attests to the fact that chipmakers are looking for... » read more

New Tools Enabling The Internet of Things


Last week I attended CDNLive Boston as a speaker and was really looking forward to the keynote given by Samuel H. Fuller, CTO and VP of R&D at Analog Devices, called “The Third Exponential Wave and the Challenges Ahead”. It was great to see, re-affirmed by Dr. Fuller, a lot of my thoughts about the Internet of Things and how it requires new tools in EDA. This, by the way, conveniently t... » read more

Conferences, Education And The Press


The EDA industry once organized itself around conferences. The Design Automation Conference (DAC) marked the time of the year when new product announcements came out thick and fast, and it was difficult to keep up with the stream of press releases. Companies with nothing to announce were viewed as deficient. New products were demonstrated in secrecy in the back rooms of the suites at the confer... » read more

Productivity And The IoT


The market for devices that connect almost everything to the [getkc id="76" comment="Internet of Things"] is projected to explode, creating opportunities for companies that haven’t been traditional chip developers to decide to start developing devices. Semiconductor Engineering sat down to discuss this topic with Jack Guedj, corporate VP of Tensilica products at [getentity id="22032" e_name="... » read more

I Have Seen The Future


We recently concluded an online survey that measured design challenges and general sentiment regarding how they can be addressed, with some specific forward-looking queries. The title of the survey was “Big Data, the Cloud and Internet of (Silicon) Things.” We essentially asked our survey respondents to look into the future. We got an excellent response to this survey, with lots of thoughtf... » read more

Designing In The Dark


While power optimization has received significant focus recently, it is still largely a hidden cost to most hardware and software engineers. A significant problem is the lack of visibility into the impact of decisions while decisions are being made. Often an engineer working on a system will have no practical way of measuring the impact of their design decisions on the system power consumption.... » read more

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