March 2015 - Semiconductor Engineering

Architecting For Optimal Interface IP Integration
By Ann Mutschler - 31 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the design and integration of complex interface IP with Ty Garibay, vice president of engineering at [getentity id="22849" e_name="Altera"]; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Saman Sadr, director of analog design... » read more

Manufacturing Bits: March 31
By Mark LaPedus - 31 Mar, 2015 - Comments: 0

Shish kebab nano necklaces Using a directed self-assembly (DSA) process, Georgia Institute of Technology has developed a method to make nanometer-scale, chip-based necklaces. The technique could enable organic-inorganic structures, which resemble a tiny shish kebab or a centipede. The structures are made with various materials, such as semiconductors, magnetics, ferroelectrics and others. ... » read more

System Bits: March 31
By Ann Mutschler - 31 Mar, 2015 - Comments: 0

Virtual nose reduces video game simulator sickness While virtual reality games often cause simulator sickness – inducing vertigo and sometimes nausea — new research by Purdue University points to a potential strategy to ease the affliction: adding a virtual nose. They explained that a number of physiological systems control the onset of simulator sickness including a person's overall se... » read more

Power/Performance Bits: March 31
By Jesse Allen - 31 Mar, 2015 - Comments: 0

Reusable gallium arsenide wafers A manufacturing process developed by Stanford researchers could dramatically reduce the cost of gallium arsenide electronics, potentially opening up new applications for the material. In the search for silicon's replacement, gallium arsenide (GaAs) has much to offer on performance. It's faster than silicon, less noise, and features a wide direct band gap�... » read more

Challenges Mount For Patterning And Masks
By Mark LaPedus - 30 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief executive at [getentity id="228... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 27 Mar, 2015 - Comments: 0

Intel is in talks to buy Altera, according to The Wall Street Journal. If a deal is reached, Intel would enter the FPGA market amid a slowdown in its core processors business. Intel would also secure its largest foundry customer in Altera. For years, Altera’s sole foundry was TSMC. Then, not long ago, Altera selected Intel as its foundry partner for 14nm. TSMC still handles 20nm and above wor... » read more

Week 42: Celebrating The 50th Anniversary Of Moore’s Law At DAC
By Anne Cirkel - 27 Mar, 2015 - Comments: 0

April 19th will mark the 50th anniversary of Gordon Moore’s now famous paper in Electronics Magazine predicting that the number of transistors on a chip will double every year. In 1975, Moore—Intel’s co-founder—revised the period to every two years, and it is still holding true. Moore’s Law not only became a legendary prediction and long-term planning guide for the semiconductor indus... » read more

Architecturally Optimizing Memory Bandwidth
By Ann Mutschler - 27 Mar, 2015 - Comments: 0

Making sure that an SoC’s [getkc id="22" kc_name="memory"] bandwidth is optimized is a crucial part of the design process today given its significance toward overall system performance. There are many ways to approach this issue, and all of them can have a direct bearing on the competitiveness of a chip in terms of both power and performance. So where should you start? “Number one, c... » read more

The Week In Review: Design/IoT
By Jesse Allen - 27 Mar, 2015 - Comments: 0

Tools Mentor Graphics uncorked its new IC, package, and PCB co-design and optimization product. It includes a formal flow for ball grid array ball-map planning and optimization based on an "intelligent pin" concept and a multi-mode connectivity management system for cross-domain pin-mapping and system level cross-domain logical verification. Synopsys released a new tool for designing ASIP... » read more

Playing With Bubbles
By Ed Sperling - 26 Mar, 2015 - Comments: 0

The first is in the social media world, where there simply are too many sites for a fixed population of users. Much has been written about this trend, including in this blog, and the big question is whether there is enough new business in new markets such as the IoT to soften the landing. The IoT has a long way to go, and a long way to grow. That growth will propel everything from the desig... » read more

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