May 2015 - Semiconductor Engineering

The Week In Review: Design/IoT
By Jesse Allen - 29 May, 2015 - Comments: 0

Mergers & Acquisitions Synopsys' list of security acquisitions grew with a definitive agreement to buy certain assets of Quotium, including the interactive application security testing product Seeker and its R&D team. The acquisition builds on static analysis technology from Coverity and Codenomicon's fuzz testing and software vulnerability assessment tools. Terms of the deal have no... » read more

Week 51: Who’s Driving To DAC?
By Anne Cirkel - 29 May, 2015 - Comments: 0

It’s come to the point where I’m counting the days to DAC – especially nerve wracking considering how much I still have to do to get ready. Just this morning I spoke with Jeff Massimilla and Craig Smith about their Wednesday morning keynote dialogue on connected cars. Helping pull together #52DAC, which includes loads of excellent content on automotive systems, has driven home (sorry) how... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 29 May, 2015 - Comments: 0

Merger and acquisition activity continues to heat up across the semiconductor industry. On one front, Avago Technologies continues on its acquisition spree. And on another front, NXP Semiconductors is moving to spin off its RF power business. And there are other deals in the works as well, including Intel’s proposed move to buy Altera. Weston Twigg, an analyst with Pacific Crest Securities... » read more

Avago Buys Broadcom; NXP Spins Off RF Power Unit
By Mark LaPedus - 28 May, 2015 - Comments: 0

Merger and acquisition activity continues to heat up across the semiconductor industry. On one front, Avago Technologies continues on its acquisition spree. And on another front, NXP Semiconductors is moving to spin off its RF power business. And there are other deals in the works as well, including Intel's proposed move to buy Altera. What’s driving the wave of M&A activity? The sem... » read more

When Things Go Wrong Even When You’re Doing the Right Thing
By Joseph Hupcey III - 28 May, 2015 - Comments: 0

By Kurt Takara and Joe Hupcey III “Isolation. Retention. Level shifters. Dynamic voltage scaling. I’m doing all the right things to reduce the power consumption of my design by adding all of this power control logic. But because of this new low power circuitry, I’m seeing fresh clock domain crossing (CDC) problems that are making my design do all the wrong things; and my trusty old low... » read more

M&A Season Now Officially Open
By Ed Sperling - 28 May, 2015 - Comments: 0

A year ago many people were making jokes quite openly about the IoT. It wasn't uncommon to hear quips about the Internet of Nothing, the Internet of Disconnected Things, the Internet of Cars, or some other variant that questioned just how connected everything would become. The tenor of the conversation has changed significantly in the past year. The jokes are fewer, the stakes are higher. An... » read more

What’s Different At 16/14nm?
By Ed Sperling - 28 May, 2015 - Comments: 0

Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

Memory Design At 16/14nm
By Brian Bailey - 28 May, 2015 - Comments: 0

As we get older the memory may start to fade, but that is not a viable option if we are talking about embedded memory. Chips contain increasing amounts of memory, and for many designs memory consumes more than half of the total chip area. “At 28nm we saw a few people with greater than 400Mbits of memory on chip,” says Prasad Saggurti, product marketing manager for Embedded Memory IP at [... » read more

The Interconnect Bottleneck
By Ann Mutschler - 28 May, 2015 - Comments: 0

With communications playing a crucial role in the design and performance of multi-core SoCs, various interconnect structures have been proposed as promising solutions to simplify and optimize SoC design. However, sometimes things don’t go as planned and the interconnect becomes the bottleneck. “Under high utilization cases the DRAM will be over-constrained with requests from all the a... » read more

Full Coverage Or Full Monty
By Brian Bailey - 28 May, 2015 - Comments: 1

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: Are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

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