January 2016 - Page 2 of 10 - Semiconductor Engineering

Are Chips Getting More Reliable?
By Ed Sperling - 28 Jan, 2016 - Comments: 4

Reliability is emerging as a key metric in the semiconductor industry, alongside of power, performance and cost, but it also is becoming harder to measure and increasingly difficult to achieve. Most large semiconductor companies look at reliability in connection with consumer devices that last several years before they are replaced, but a big push into automotive, medical and industrial elec... » read more

Predictions For 2016: Tools and Flows
By Brian Bailey - 28 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Enablement For A Decade Of Innovation
By Frank Schirrmeister - 28 Jan, 2016 - Comments: 0

As I do every January, I am looking back 5, 10, and 15 years to see what predictions did and did not turn out to be right, and how that relates to design technologies enabling those developments. Looking back five years reveals just how key system-development technologies were for what IEEE dubbed the “Top 11 Technologies of the Decade”. Looking back 10 years shows how they enabled communic... » read more

Reprogrammable, Reprogrammable, Reprogrammable
By Aldec - 28 Jan, 2016 - Comments: 0

By Alex Grove I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal. Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree ... » read more

IC Compiler II Multi-Level Physical Hierarchy Floorplanning
By Synopsys - 27 Jan, 2016 - Comments: 0

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

Beyond UVM Registers — Better, Faster, Smarter
By Mentor, a Siemens Business - 27 Jan, 2016 - Comments: 0

Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register layer with good success. But the UVM Register layer has many moving parts and intricate details. It can be difficult to adopt and it can be difficult to model complex registers. It is a complex syst... » read more

Debug: Last Bastion Of Automation
By Brian Bailey - 27 Jan, 2016 - Comments: 0

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Finding CDC Issues Before They Find You
By Aldec - 27 Jan, 2016 - Comments: 0

Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated. To read more, cl... » read more

Blog Review: Jan. 27
By Jesse Allen - 27 Jan, 2016 - Comments: 0

There's an ocean of possibilities for transistors and interconnects at the 5nm node, says Cadence's Paul McLellan – but will any of them be feasible in time? How would you design R2-D2? Mentor's Joe Hupcey III lays out what low power techniques he thinks the Star Wars droid might require. It's not all clear skies in the world of FinFETs, as Synopsys' Graham Etchells continues his series... » read more

System Bits: Jan. 26
By Ann Mutschler - 26 Jan, 2016 - Comments: 0

Precisely controlling graphene molecules Researchers at UCLA’s California NanoSystems Institute have found that in the same way gardeners may use sheets of plastic with strategically placed holes to allow plants to grow but keep weeds from taking root, the same basic approach can be applied in terms of placing molecules in the specific patterns they need within tiny nanoelectronic devices, w... » read more

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