February 2017 - Page 2 of 10 - Semiconductor Engineering

Better Code With RTL Linting And CDC Verification
By Sergei Zaychenko - 23 Feb, 2017 - Comments: 0

Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

IP Qualification During RTL Synthesis
By Sudhakar Jilla - 23 Feb, 2017 - Comments: 0

By Sudhakar Jilla and Arvind Narayanan The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical design, which can introduce unwanted schedule risk into the design process. Much of the risk of IP development can be mitigated by using new physical synthesis... » read more

Software Modeling And KPI
By Pat Sheridan - 23 Feb, 2017 - Comments: 0

In Software Modeling Goes Mainstream, Ed Sperling recently wrote how chipmakers are applying use case modeling techniques to better understand the interactions between software and hardware and how they impact system performance and energy efficiency. As the software content for multicore SoCs grows, these interactions are becoming increasingly complex. For system designers and SoC architect... » read more

Custom Hardware Thriving
By Ann Mutschler - 23 Feb, 2017 - Comments: 0

In the early days of the IoT, predictions about the commoditization of hardware and the end of customized hardware were everywhere. Several years later, those predictions are being proven wrong. Off-the-shelf components have not replaced customized hardware, and software has not dictated all designs. In fact, in many cases the exact opposite has happened. And where software does play an elev... » read more

Advanced ASICs Are A Team Sport
By Mike Gianfagna - 23 Feb, 2017 - Comments: 0

The recent Super Bowl proved that a team with conviction and focus can do anything. This notion comes in handy when you think about the nearly impossible job of designing and manufacturing an advanced ASIC – in finFET technologies, with an interposer, multiple die, and never-before-proven throughput rates. For these kind of advanced technologies, it does take a village. What works is open, tr... » read more

What Does AI Really Mean?
By Ed Sperling - 23 Feb, 2017 - Comments: 0

Seth Neiman, chairman of eSilicon, founder of Brocade Communications, and a board member and investor in a number of startups, sat down with Semiconductor Engineering to talk about advances in AI, what's changing, and how it ultimately could change our lives. What follows are excerpts of that conversation. SE: How far has AI progressed? Neiman: We’ve been working with AI since the mid 1... » read more

Fault Simulation Reborn
By Brian Bailey - 23 Feb, 2017 - Comments: 0

Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2017
By Frank Schirrmeister - 23 Feb, 2017 - Comments: 0

DVCon 2017 is upon us next week and even though it is called the “Design and Verification” conference, it is rising more and more to the system level. One of the aspects of interest is how verification seems to simultaneously become broader—covering more aspects to verify like software, power and performance—while also becoming more deep when it comes to application domains and their sp... » read more

Find Your Way To San Jose Next Week… For DVCon, Of Course!
By Dave Kelf - 23 Feb, 2017 - Comments: 0

If you’re asked “Do you know the way to San Jose?” in the next few days, chances are it’s a newbie to DVCon. Everyone else in chip design verification knows the way to the annual Design and Verification Conference and Exhibition about to convene at the San Jose DoubleTree Hotel. This year’s program is stacking up to be an insightful and educational four days of tutorials, paper ses... » read more

The Path To (Virtually) Zero Defective Parts Per Million
By Synopsys - 22 Feb, 2017 - Comments: 0

Despite thorough wafer and package testing, a small number of defective ICs can make their way into systems. These test "escapes" often return as field failures, increasing costs and eroding profit margins. They can also present a hazard if deployed in safety-critical systems, which is why companies purchasing semiconductors for automotive, medical, or aerospace applications often demand a zero... » read more

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