March 2018 - Semiconductor Engineering

Switching a Perpendicular Ferromagnetic Layer by Competing Spin Currents
By Technical Paper Link - 31 Mar, 2018 - Comments: 0

ABSTRACT "An ultimate goal of spintronics is to control magnetism via electrical means. One promising way is to utilize a current-induced spin-orbit torque (SOT) originating from the strong spin-orbit coupling in heavy metals and their interfaces to switch a single perpendicularly magnetized ferromagnetic layer at room temperature. However, experimental realization of SOT switching to date req... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 30 Mar, 2018 - Comments: 0

Chipmakers 3D NAND continues to gain steam, but is the industry headed towards a capacity glut in the overall NAND market? Time will tell. In any case, Toshiba is moving forward with its plans to invest in its Fab 6 facility in Japan. The fab will produce the company’s 96-layer 3D NAND devices. Then, Samsung plans to invest $7 billion to double the production capacity for NAND flash memor... » read more

The Week in Review: IoT
By Jeff Dorsch - 30 Mar, 2018 - Comments: 0

Regulation The Consumer Product Safety Commission is accepting public comments on “potential safety issues and hazards associated with Internet-connected consumer products.” The agency is concerned about “unexpected operating conditions” with Internet of Things devices, along with hacking that could start fires through a stovetop or grill, and the potential compromising of home safety ... » read more

The Week In Review: Design
By Jesse Allen - 30 Mar, 2018 - Comments: 0

Market research firm IC Insights says fabless IC suppliers accounted for 27% of the world’s IC sales in 2017—an increase from 18% ten years earlier in 2007. U.S. companies accounted for the greatest share of fabless IC sales last year at 53% (down, however, from 2010's share of 69%). Since 2010, the largest fabless IC marketshare increase has come from the Chinese suppliers, which captured ... » read more

What Happened To Nanoimprint Litho?
By Mark LaPedus - 29 Mar, 2018 - Comments: 4

Nanoimprint lithography (NIL) is re-emerging amid an explosion of new applications in the market. Canon, EV Group, Nanonex, Suss and others continue to develop and ship NIL systems for a range of markets. NIL is different than conventional lithography and resembles a stamping process. Initially, a lithographic system forms a pattern on a template based on a pre-defined design. Then, a separa... » read more

Self-Aligned Block And Fully Self-Aligned Via For iN5 Metal 2 Self-Aligned Quadruple Patterning
By Coventor - 29 Mar, 2018 - Comments: 0

This paper assesses Self-Aligned Block (SAB) and Fully Self-Aligned Via (FSAV) approaches to patterning using a iN5 (imec node 5 nm) vehicle and Metal 2 Self-Aligned Quadruple Patterning. We analyze SAB printability in the lithography process using process optimization, and demonstrate the effect of SAB on patterning yield for a (8 M2 lines x 6 M1 lines x 6 Via) structure. We show that FSAV, co... » read more

Who’s Responsible For Security?
By Ed Sperling - 29 Mar, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss security issues and how to fix them with Mark Schaeffer, senior product marketing manager for secure solutions at Renesas Electronics; Haydn Povey, CTO of Secure Thingz; Marc Canel, vice president of security systems and technologies at [getentity id="22186" comment="Arm"]; Richard Hayton, CTO of Trustonic; Anders Holmberg, director of corporate dev... » read more

Improving Patterning Yield At The 5nm Semiconductor Node
By Benjamin Vincent - 29 Mar, 2018 - Comments: 0

Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconduct... » read more

Blog Review: March 28
By Jesse Allen - 28 Mar, 2018 - Comments: 0

Mentor's Joe Hupcey III and Jin Hou explain how to use the Open Verification Language (OVL) library of assertions to build an effective formal testbench. In a video, Cadence's Marc Greenberg discusses the benefits of moving non-volatile memory from the SSD to the DDR bus and possible new storage-class memories. Synopsys' Anders Nordstrom argues that security can no longer be ignored when ... » read more

Going Deep Or Broad With Formal?
By Ann Mutschler - 28 Mar, 2018 - Comments: 0

Whether to apply [getkc id="33" comment="formal verification"] technology to semiconductor design broadly or deeply is a tough question. It hinges on what is the best way to achieve maximum ROI. Do you want to identify hard to find bugs, and get a certain level of confidence about a block? Where should the effort be placed? Is it by going deep, meaning a team of specialists or experts must b... » read more

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