2D Semiconductor Materials Creep Toward Manufacturing

As transistors scale down, they need thinner channels to achieve adequate channel control. In silicon, though, surface roughness scattering degrades mobility, limiting the ultimate channel thickness to about 3nm.

Two-dimensional transition metal dichalcogenides (TMDs), such as MoS₂ and WSe₂, are attractive in part because they avoid this limitation. With no out-of-plane dangling bonds and atomically smooth interfaces, TMDs avoid scattering-induced mobility degradation even at sub-angstrom thicknesses.^⁠[1]

Still, TMDs represent a radical change from the silicon, or even silicon-germanium, status quo. Material growth, contact formation, and device fabrication all differ from the corresponding silicon processes. Right now, fundamental materials research and device development are proceeding in parallel. Materials and processes that give good results in laboratory devices may not be suitable for volume manufacturing.

For example, most TMD device demonstrations to date have relied on layer transfer techniques. This approach starts with a freestanding film, either grown on a compatible substrate like sapphire or exfoliated from bulk material. Any of several methods can be used to transfer the film to a prepared destination substrate that may already include a bottom gate structure.

Layer transfer poses obvious cost and yield challenges. In work presented at December’s IEEE International Electron Device Meeting (IEDM), C. J. Dorow and colleagues at Intel showed that that single-gate MoS₂ devices suffered from performance degradation attributable to the transfer process. They observed TMD delamination in the source and drain regions. A sacrificial low-k dielectric layer left residue at the TMD/oxide interface, as well.^⁠[2] Semiconductor fabs would prefer the flexibility and cost effectiveness of a more “silicon-like” process, with TMD deposition directly on the destination substrate.

Generally speaking, TMD growth presents a tradeoff between film quality and the desire to minimize channel thickness. Both atomic-level deposition (ALD) dielectrics and TMDs grown with chemical vapor deposition (CVD) are prone to pinholes and other defects. Still, several papers presented at December’s IEEE IEDM showed that the industry is making progress toward direct deposition of TMDs. For instance, Xinhang Shi and colleagues at Peking University used low-pressure CVD to grow WSe₂ bilayers directly on SiO₂. The very high temperature process (890°C) gave devices with record high I_ds of 425 μA/μm.^⁠[3] Film properties were independent of the oxide thickness. Alternatively, TSMC’s Yun-Yan Chung and colleagues used a tungsten pad as a seed layer for growth of WS₂, building devices with two and three stacked channels.^⁠[4]

Fig. 1: TEM cross section of monolayer MoS2 nanosheet fully surrounded by the gate stack. Smaller images show EDX elemental mapping. Source: Y-Y Chung et. al.

Dielectrics for doping and threshold voltage control
A complete CMOS process is more than simply depositing the channel material. The process must also facilitate both hole and electron conduction. In TMDs, doping, dielectric deposition, and V_th tuning are inextricable from each other. Because doping the semiconductor itself is not currently possible, devices depend on cap layers to modulate conduction and deliver nFET or pFET behavior. Even once suitable materials are identified, the two-dimensional character of the TMD surface complicates cap layer deposition. There are very few potential nucleation sites for deposited oxides other than grain boundaries and other defects.

WSe₂ is an ambipolar material, which means the Fermi level shifts between the valence and conduction bands in the presence of an applied field. Thus, the same material can conduct either electrons or holes.^⁠[5]

Several different groups at TSMC have been studying WSe₂ conduction and doping from different angles. One group used an oxygen plasma to convert WSe₂ semiconducting monolayers to WO_x. The process was self-limiting, leaving underlying WSe₂ material untouched, and the resulting doping level depended on the interlayer coupling in the starting material. Thicker starting material gave a higher valence band edge, leading to higher doping after conversion to an oxide.^⁠[6] Another TSMC group, in work presented by Ang-Sheng Chou, used MoO_x cap layers for pFET devices and SiON_x for nFET devices. Together with novel contact technology, discussed below, these cap layers delivered some of the best TMD transistor results to date.[7]^⁠

At Purdue University, researchers used hexagonal boron nitride (hBN) as an interfacial layer to facilitate dielectric deposition. Their work emphasized the distinction between “defects” and “traps.” As they explained, defects can occur both within the bulk of the dielectric and at the dielectric-semiconductor interface. However, a defect only becomes a trap if the Fermi level crosses the defect energy band. Encapsulating monolayer MoS₂ in hBN reduced the subthreshold swing and increased V_th, implying that interface traps were either eliminated or deactivated. The hBN layer appeared to block absorbates on the TMD film, a potential source of charge traps.

Unfortunately, hBN is not a suitable dielectric in itself. It’s also a graphite-like material with weak out-of-plane bonding, making growing a dielectric directly on hBN challenging. The Purdue group used a tantalum seed layer for dielectric deposition. Relative to the more common aluminum seed, they saw less subthreshold swing degradation and a reduced V_th shift.^⁠[8]

Fig. 2: By systematically analyzing key process parameters, researchers at TSMC integrated hafnium-based dielectrics with CVD-grown MoS₂ to build a top-gate nFET with EOT ~1 nm and nearly ideal subthreshold swing. This work is especially noteworthy because depositing pinhole-free dielectrics on TMDs is notoriously difficult. Source: T. -E. Lee et al. [9]

Stacking channels and making contact
Practical devices are likely to see still further process complexity due to the need for stacked channels. A single TMD monolayer cannot carry as much current as a silicon nanosheet, so devices will need several stacked TMD sheets. As in stacked silicon nanosheets, minimizing spacing between sheets reduces parasitic capacitance.

Fig. 3: Two-dimensional MoS₂ stacked nanoribbon structure. Source: C. J. Dorow/Intel [2]

Because TMD layers are so thin, Yun-Yan Chung’s group pointed out that mechanical stability can also be an issue. They used a sacrificial dielectric to improve stiffness and prevent sagging during fabrication. The inner spacer and metal contacts help to anchor the channel in the finished device.

The last step in TMD transistor construction, making contact with the rest of the circuit, has received intense research attention since these devices were proposed. Still, contact and spacer resistance account for as much as 80% of the overall device resistance in 2D transistors, a much more significant contribution than silicon contacts and spacers. Recent work using semimetals like bismuth and antimony has given good results for nFETs, but pFET contacts remain an unsolved problem.

As Ang-Sheng Chou’s group explained, most proposed contacts have an unfortunate band alignment for hole conduction. Their work took advantage of the ambipolar nature of WSe₂ to use a single antimony/platinum stack for both nFET and pFET devices. Antimony (Sb, work function 4.4 eV) provides a buffer layer, minimizing damage to the underlying semiconductor. Platinum (Pt, work function 5.6 eV) tunes the work function. The ratio of the two materials is adjustable to achieve the desired work function for both nFETs and pFETs. In the end, they reported low barrier heights, low contact resistance, and on current of about 150 μA/μm for both electrons and holes.

What’s next for 2D semiconductors?
Even more than the results themselves, the proliferation of reporting from companies like Intel and TSMC demonstrates that TMD-based transistors are serious candidates to succeed silicon. While the industry in the past couple years has begun to clarify the potential design of such devices — either MoS₂ or WSe₂ channels, with semimetal contacts — robust, manufacturable fabrication processes have yet to emerge.

References

1. Luisier et al., “First-principles simulations of 2-D semiconductor devices: Mobility, I-V characteristics, and contact resistance,” 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 5.4.1-5.4.4, doi: 10.1109/IEDM.2016.7838353.
2. C. J. Dorow et al., “Gate length scaling beyond Si: Mono-layer 2D Channel FETs Robust to Short Channel Effects,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 7.5.1-7.5.4, doi: 10.1109/IEDM45625.2022.10019524.
3. Shi et al., “High-Performance Bilayer WSe₂ pFET with Record Ids = 425 μA/μm and Gm = 100 at μS/μm Vds = -1 V By Direct Growth and Fabrication on SiO2 Substrate,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 7.1.1-7.1.4, doi: 10.1109/IEDM45625.2022.10019404.
4. Y.-Y. Chung et al., “First Demonstration of GAA Monolayer-MoS₂ Nanosheet nFET with 410μA μm ID 1V VD at 40nm gate length,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 34.5.1-34.5.4, doi: 10.1109/IEDM45625.2022.10019563.
5. Z. Wang, Q. Li, Y. Chen, et al. The ambipolar transport behavior of WSe₂ transistors and its analogue circuits. NPG Asia Mater 10, 703–712 (2018). https://doi.org/10.1038/s41427-018-0062-1
6. Y. T. Hung et al., “pMOSFET with CVD-grown 2D semiconductor channel enabled by ultra-thin and fab-compatible spacer doping,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 7.3.1-7.3.4, doi: 10.1109/IEDM45625.2022.10019321.
7. A.-S. Chou et al., “High-Performance Monolayer WSe₂ p/n FETs via Antimony-Platinum Modulated Contact Technology towards 2D CMOS Electronics,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 7.2.1-7.2.4, doi: 10.1109/IEDM45625.2022.10019491.
8. -Y. Lan, J. Appenzeller and Z. Chen, “Dielectric Interface Engineering for High-Performance Monolayer MoS₂ Transistors via hBN Interfacial Layer and Ta Seeding,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 7.7.1-7.7.4, doi: 10.1109/IEDM45625.2022.10019439.
9. T. -E. Lee et al., “Nearly Ideal Subthreshold Swing in Monolayer MoS₂ Top-Gate nFETs with Scaled EOT of 1 nm,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 7.4.1-7.4.4, doi: 10.1109/IEDM45625.2022.10019552.